HD64F2149YV datasheet(534/1075 Pages) RENESAS

534 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 506 of 1044

REJ09B0280-0300

Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be

transferred next. With the I

2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0),

the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made

during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000,

the setting should be made while the SCL line is low.

The bit counter is initialized to 000 by a reset and when a start condition is detected. The value

returns to 000 at the end of a data transfer, including the acknowledge bit.

Bit 2

Bit 1

Bit 0

Bits/Frame

BC2

BC1

BC0

Synchronous Serial Format

2C Bus Format

(Initial value)

16.2.5

2C Bus Control Register (ICCR)

Bit

Initial value

Read/Write

Note: * Only 0 can be written, to clear the flag.

ICE

R/W

IEIC

R/W

MST

R/W

TRS

R/W

ACKE

R/W

SCP

BBSY

R/W

IRIC

R/(W)*

ICCR is an 8-bit readable/writable register that enables or disables the I

2C bus interface, enables or

disables interrupts, selects master or slave mode and transmission or reception, enables or disables

acknowledgement, confirms the I

2C bus interface bus status, issues start/stop conditions, and

performs interrupt flag confirmation.

ICCR is initialized to H'01 by a reset and in hardware standby mode.

HD64F2149YV 数据表(PDF) 534 Page - Renesas Technology Corp

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