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HD64F2149YV 数据表(PDF) 592 Page - Renesas Technology Corp

部件名 HD64F2149YV
功能描述  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

HD64F2149YV 数据表(HTML) 592 Page - Renesas Technology Corp

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Section 17 Keyboard Buffer Controller
Rev. 3.00 Jan 18, 2006 page 564 of 1044
REJ09B0280-0300
Bit 1—Parity Error (PER): Indicates that an odd parity error has occurred.
Bit 1
PER
Description
0
[Clearing condition]
(Initial value)
Read PER when PER =1, then write 0 in PER
1
[Setting condition]
When an odd parity error occurs
Bit 0—Keyboard Stop (KBS): Indicates the receive data stop bit. Valid only when KBF = 1.
Bit 0
KBS
Description
0
0 stop bit received
(Initial value)
1
1 stop bit received
17.2.2
Keyboard Control Register L (KBCRL)
Bit
76543210
KBE
KCLKO
KDO
—
RXCR3
RXCR2
RXCR1
RXCR0
Initial value
01110000
Read/Write
R/W
R/W
R/W
—
RRRR
KBCRL is an 8-bit readable/writable register that enables the receive counter count and controls
the keyboard buffer controller pin output.
KBCRL is initialized to H'70 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bit 7—Keyboard Enable (KBE): Enables or disables loading of receive data into the keyboard
data buffer register (KBBR).
Bit 7
KBE
Description
0
Loading of receive data into KBBR is disabled
(Initial value)
1
Loading of receive data into KBBR is enabled



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