HD64F2149YV datasheet(595/1075 Pages) RENESAS

595 / 1075 page

Section 17 Keyboard Buffer Controller

Rev. 3.00 Jan 18, 2006 page 567 of 1044

REJ09B0280-0300

17.2.4

Module Stop Control Register (MSTPCR)

MSTP15

R/W

Bit

Initial value

Read/Write

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRH

MSTPCRL

MSTPCR, comprising two 8-bit readable/writable register, performs module stop mode control.

When the MSTP2 bit is set to 1, the keyboard buffer controller halts and enters module stop mode.

See section 24.5, Module Stop Mode, for details.

MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

MSTPCRL Bit 2—Module Stop (MSTP2): Specifies keyboard buffer controller module stop

mode.

MSTPCRL

Bit 2

MSTP2

Description

Keyboard buffer controller module stop mode is cleared

Keyboard buffer controller module stop mode is set

(Initial value)

17.3

Operation

17.3.1

Receive Operation

In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and

inputs on the H8S/2169 or H8S/2149 chip (system) side. KD receives a start bit, 8 data bits (LSB-

first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is low. A

sample receive processing flowchart is shown in figure 17.3, and the receive timing in figure 17.4.

HD64F2149YV 数据表(PDF) 595 Page - Renesas Technology Corp

HD64F2149YV 数据表(HTML) 595 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载