HD64F2149YV datasheet(625/1075 Pages) RENESAS

625 / 1075 page

Section 18A Host Interface X-Bus Interface (XBS)

Rev. 3.00 Jan 18, 2006 page 597 of 1044

REJ09B0280-0300

Table 18A.7 Fast A20 Gate Output Signal

HA0

Data/Command

Internal CPU

Interrupt Flag

GA20

(P81)

Remarks

H'D1 command

1 data*

H'FF command

Q (1)

Turn-on sequence

H'D1 command

0 data*

H'FF command

Q (0)

Turn-off sequence

1/0

H'D1 command

1 data*

Command other than H'FF

and H'D1

Q (1)

Turn-on sequence

(abbreviated form)

1/0

H'D1 command

0 data*

Command other than H'FF

and H'D1

Q (0)

Turn-off sequence

(abbreviated form)

H'D1 command

Command other than H'D1

Cancelled sequence

H'D1 command

Retriggered sequence

H'D1 command

Any data

H'D1 command

1/0

Q(1/0)

Consecutively executed

sequences

Notes: 1. Arbitrary data with bit 1 set to 1.

2. Arbitrary data with bit 1 cleared to 0.

18A.3.4 Host Interface Pin Shutdown Function

Host interface output can be placed in the high-impedance state according to the state of the

HIFSD pin. Setting the SDE bit to 1 in the SYSCR2 register when the HI12E bit is set to 1 enables

the HIFSD pin. The HIF constantly monitors the HIFSD pin, and when this pin goes low, places

the host interface output pins (HIRQ1, HIRQ11, HIRQ12, HIRQ3, HIRQ4, and GA20) in the

high-impedance state. At the same time, the host interface input pins (

CS1, CS2 or ECS2, CS3,

CS4, IOW, IOR, and HA0) are disabled (fixed at the high input state internally) regardless of the

pin states, and the signals of the multiplexed functions of these pins (input block) are similarly

fixed internally. As a result, the host interface I/O pins (HDB7 to HDB0) also go to the high-

impedance state.

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