HD64F2149YV datasheet(629/1075 Pages) RENESAS

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Section 18A Host Interface X-Bus Interface (XBS)

Rev. 3.00 Jan 18, 2006 page 601 of 1044

REJ09B0280-0300

18A.5 Usage Note

Note the following when using the XBS function.

(1) Transmitting/receiving sequence of the transfer between the host and slave processors

The host interface provides buffering of asynchronous data from the host and slave processors,

but an interface protocol must be followed to implement necessary functions and avoid data

contention. For example, if the host and slave processors try to access the same input or output

data register simultaneously, the data will be corrupted. Interrupts can be used to design a

simple and effective protocol.

(2) Data contention on the host interface data bus (HDB)

When the HIF function is used and channel 3 or channel 4 is not used, the following condition

must be satisfied.

(1) The unselected channel pins must be fixed at a high level.

(2) Port B must not be read.

(3) Through-current at the pins

CS1 to CS4

Also, if two or more of pins

CS1 to CS4 are driven low simultaneously in attempting IDR or

ODR access, signal contention will occur within the chip, and a through-current may result.

This usage must therefore be avoided.

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