HD64F2149YV datasheet(725/1075 Pages) RENESAS

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Section 22 ROM

Rev. 3.00 Jan 18, 2006 page 697 of 1044

REJ09B0280-0300

22.4.5

The registers used to control the on-chip flash memory when enabled are shown in table 22.5.

In order for these registers to be accessed, the FLSHE bit must be set to 1 in STCR.

Table 22.5

Flash Memory Registers

Abbreviation

R/W

Initial Value

Address*

Flash memory control register 1

FLMCR1*

R/W*

H'80

H'FF80*

Flash memory control register 2

FLMCR2*

R/W*

H'00*

H'FF81*

Erase block register 1

EBR1*

—*

H'00*

H'FF82*

Erase block register 2

EBR2*

R/W*

H'00*

H'FF83*

Serial/timer control register

STCR

R/W

H'00

H'FFC3

Notes: 1. Lower 16 bits of the address.

2. Flash memory registers share addresses with other registers. Register selection is

performed by the FLSHE bit in the serial/timer control register (STCR).

3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and

writes are invalid.

4. When the SWE bit in FLMCR1 is not set, these registers are initialized to H'00.

5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid

for these registers, the access requiring 2 states.

22.5

22.5.1

Flash Memory Control Register 1 (FLMCR1)

Bit

76543210

FWE

SWE

——

Initial value

10000000

Read/Write

R/W

——

R/W

FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode

or erase-verify mode is entered by setting SWE to 1. Program mode is entered by setting SWE to

1, then setting the PSU bit in FLMCR2, and finally setting the P bit. Erase mode is entered by

setting SWE to 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is

initialized to H'80 by a reset, and in hardware standby mode, software standby mode, subactive

mode, subsleep mode, and watch mode. When on-chip flash memory is disabled, a read will return

H'00, and writes are invalid.

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