HD64F2149YV datasheet(730/1075 Pages) RENESAS

730 / 1075 page

Section 22 ROM

Rev. 3.00 Jan 18, 2006 page 702 of 1044

REJ09B0280-0300

22.5.4

Serial/Timer Control Register (STCR)

Bit

543210

IICS

IICX1

IICX0

IICE

FLSHE

—

ICKS1

ICKS0

Initial value

000000

Read/Write

R/W

STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode

(when the on-chip IIC option is included), and on-chip flash memory, and also selects the TCNT

input clock. For details on functions not related to on-chip flash memory, see section 3.2.4, Serial

Timer Control Register (STCR), and descriptions of individual modules. If a module controlled by

STCR is not used, do not write 1 to the corresponding bit.

STCR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 to 4—I

2C Control (IICS, IICX1, IICX0, IICE): These bits control the operation of the I2C

bus interface. For details, see section 16, I

2C Bus Interface.

Bit 3—Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables

read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash

memory control registers are deselected. In this case, the flash memory control register contents

are retained.

Bit 3

FLSHE

Description

Flash memory control registers deselected

(Initial value)

Flash memory control registers selected

Bit 2—Reserved: Do not write 1 to this bit.

Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits control 8-bit timer

operation. See section 12, 8-Bit Timers, for details.

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