HD64F2149YV datasheet(886/1075 Pages) RENESAS

部件名	HD64F2149YV

功能描述	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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886 / 1075 page

Appendix A Instruction Set

Rev. 3.00 Jan 18, 2006 page 858 of 1044

REJ09B0280-0300

A.5

Bus States during Instruction Execution

Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See

table A.4.

How to Read the Table:

Instruction

JMP@aa:24

R:W 2nd

Internal

operation,

2 state

R:W EA

End of instruction

Order of execution

Read effective address (word-size read)

No read or write

Read 2nd word of current instruction

(word-size read)

Legend:

R:B

Byte-size read

R:W

Word-size read

W:B

Byte-size write

W:W

Word-size write

Transfer of the bus is not performed immediately after this cycle

2nd

Address of 2nd word (3rd and 4th bytes)

3rd

Address of 3rd word (5th and 6th bytes)

4th

Address of 4th word (7th and 8th bytes)

5th

Address of 5th word (9th and 10th bytes)

Start address of instruction following executing instruction

Effective address

VEC

Vector address

HD64F2149YV 数据表(PDF) 886 Page - Renesas Technology Corp

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