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HD64F2149YV 数据表(PDF) 921 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 921 Page - Renesas Technology Corp |
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921 / 1075 page ![]() Appendix B Internal I/O Registers Rev. 3.00 Jan 18, 2006 page 893 of 1044 REJ09B0280-0300 B.3 Functions DACR—D/A Control Register H'FFFA D/A Converter Register name Address to which the register is mapped Name of on-chip supporting module Register acronym Bit numbers Initial bit values Names of the bits. Dashes (—) indicate reserved bits. Full name of bit Descriptions of bit settings Read only Write only Read and write R W R/W Possible types of access Bit Initial value Read/Write 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 — 1 — 3 — 1 — 0 — 1 — 2 — 1 — 1 — 1 — D/A enabled DAOE1 0 1 Conversion result DAE * 0 1 0 1 * DAOE0 0 1 0 1 Channel 0 and 1 D/A conversion disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled Channel 0 and 1 D/A conversion enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled D/A output enable 0 0 Analog output DA0 disabled 1 Channel 0 D/A conversion enabled. Analog output DA0 enabled D/A output enable 1 0 Analog output DA1 disabled 1 Channel 1 D/A conversion enabled. Analog output DA1 enabled |
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