HD64F2149YV datasheet(146/1075 Pages) RENESAS

146 / 1075 page

Section 5 Interrupt Controller

Rev. 3.00 Jan 18, 2006 page 118 of 1044

REJ09B0280-0300

5.3.3

Interrupt Exception Vector Table

Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.

For default priorities, the lower the vector number, the higher the priority.

Priorities among modules can be set by means of ICR. The situation when two or more modules

are set to the same priority, and priorities within a module, are fixed as shown in table 5.4.

Table 5.4

Interrupt Sources, Vector Addresses, and Interrupt Priorities

Vector Address

Interrupt Source

Origin of

Interrupt

Source

Vector

Number

Normal

Mode

Advanced

Mode

ICR

Priority

NMI

H'000E

H'00001C

High

IRQ0

External

H'0020

H'000040

ICRA7

IRQ1

H'0022

H'000044

ICRA6

IRQ2

IRQ3

H'0024

H'0026

H'000048

H'00004C

ICRA5

IRQ4

IRQ5

H'0028

H'002A

H'000050

H'000054

ICRA4

IRQ6, KIN7 to KIN0

IRQ7, KIN15 to KIN8, WUE7 to

WUE0

H'002C

H'002E

H'000058

H'00005C

ICRA3

SWDTEND (software activation

interrupt end)

DTC

H'0030

H'000060

ICRA2

WOVI0 (interval timer)

Watchdog

timer 0

H'0032

H'000064

ICRA1

WOVI1 (interval timer)

Watchdog

timer 1

H'0034

H'000068

ICRA0

Address break (PC break)

—

H'0036

H'00006C

ADI (A/D conversion end)

A/D

H'0038

H'000070

ICRB7

Reserved

—

H'003A

H'005E

H'000074

H'0000BC

Low

HD64F2149YV 数据表(PDF) 146 Page - Renesas Technology Corp

HD64F2149YV 数据表(HTML) 146 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载