HD64F2149YV datasheet(161/1075 Pages) RENESAS

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Section 5 Interrupt Controller

Rev. 3.00 Jan 18, 2006 page 133 of 1044

REJ09B0280-0300

5.5.5

Interrupt Response Times

The H8S/2149 is capable of fast word access to on-chip memory, and high-speed processing can

be achieved by providing the program area in on-chip ROM and the stack area in on-chip RAM.

Table 5.8 shows interrupt response times—the interval between generation of an interrupt request

and execution of the first instruction in the interrupt handling routine. The symbols used in table

5.8 are explained in table 5.9.

Table 5.8

Interrupt Response Times

Number of States

No.

Item

Normal Mode

Advanced Mode

Interrupt priority determination*

Number of wait states until executing

instruction ends*

1 to (19+2·S

PC, CCR stack save

2·S

Vector fetch

2·S

Instruction fetch*

2·S

Internal processing*

Total (using on-chip memory)

11 to 31

12 to 32

Notes: 1. Two states in case of internal interrupt.

2. Refers to MULXS and DIVXS instructions.

3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.

4. Internal processing after interrupt acceptance and internal processing after vector fetch.

Table 5.9

Number of States in Interrupt Handling Routine Execution

Object of Access

External Device

8-Bit Bus

16-Bit Bus

Symbol

Internal

Memory

2-State

Access

3-State

Access

2-State

Access

3-State

Access

Instruction fetch

6+2m

3+m

Branch address read

Stack manipulation

Legend:

m: Number of wait states in an external device access

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