HD64F2149YV datasheet(165/1075 Pages) RENESAS

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Section 5 Interrupt Controller

Rev. 3.00 Jan 18, 2006 page 137 of 1044

REJ09B0280-0300

5.7.3

Operation

The interrupt controller has three main functions in DTC control.

Selection of Interrupt Source: It is possible to select DTC activation request or CPU interrupt

request with the DTCE bit of DTCERA to DTCERE in the DTC.

After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the

CPU in accordance with the specification of the DISEL bit of MRB in the DTC.

When the DTC performs the specified number of data transfers and the transfer counter reaches 0,

following the DTC data transfer the DTCE bit is cleared to 0 and an interrupt request is sent to the

CPU.

Determination of Priority: The DTC activation source is selected in accordance with the default

priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC Vector Table,

for the respective priorities.

Operation Order: If the same interrupt is selected as a DTC activation source and a CPU

interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception

handling.

Table 5.10 summarizes interrupt source selection and interrupt source clearance control according

to the settings of the DTCE bit of DTCERA to DTCERE in the DTC and the DISEL bit of MRB

in the DTC.

Table 5.10

Interrupt Source Selection and Clearing Control

Settings

DTC

Interrupt Source Selection/Clearing Control

DTCE

DISEL

DTC

CPU

×∆

∆×

∆

Legend:

∆: The relevant interrupt is used. Interrupt source clearing is performed.

(The CPU should clear the source flag in the interrupt handling routine.)

O: The relevant interrupt is used. The interrupt source is not cleared.

×: The relevant bit cannot be used.

*:Don’t care

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