HD64F2149YV datasheet(239/1075 Pages) RENESAS

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Section 8 I/O Ports

Rev. 3.00 Jan 18, 2006 page 211 of 1044

REJ09B0280-0300

8.3.2

Table 8.4 shows the port 2 register configuration.

Table 8.4

Port 2 Registers

Name

Abbreviation

R/W

Initial Value

Address*

Port 2 data direction register

P2DDR

H'00

H'FFB1

Port 2 data register

P2DR

R/W

H'00

H'FFB3

Port 2 MOS pull-up control

P2PCR

R/W

H'00

H'FFAD

Note:

Lower 16 bits of the address.

Port 2 Data Direction Register (P2DDR)

P27DDR

P26DDR

P25DDR

P24DDR

P23DDR

P20DDR

P22DDR

P21DDR

Bit

Initial value

Read/Write

P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port 2. P2DDR cannot be read; if it is, an undefined value will be returned.

P2DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in

software standby mode. The address output pins maintain their output state in a transition to

software standby mode.

• Mode 1

The corresponding port 2 pins are address outputs, regardless of the P2DDR setting.

In hardware standby mode, the address outputs go to the high-impedance state.

• Modes 2 and 3 (EXPE = 1)

The corresponding port 2 pins are address outputs or PWM outputs when P2DDR bits are set

to 1, and input ports when cleared to 0. P27 to P24 are switched from address outputs to output

ports by setting the IOSE bit to 1.

P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting,

but to ensure normal access to external space, P27 should not be set as an on-chip supporting

module output pin when port 2 pins are used as address output pins.

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