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HD64F2149YV 数据表(PDF) 287 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 287 Page - Renesas Technology Corp |
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287 / 1075 page ![]() Section 8 I/O Ports Rev. 3.00 Jan 18, 2006 page 259 of 1044 REJ09B0280-0300 • Modes 2 and 3 (EXPE = 0) A port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an input port if the bit is cleared to 0. Port B Output Data Register (PBODR) Bit 7 6 543210 PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial value 0 0 000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PBODR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBODR can always be read or written to, regardless of the contents of PBDDR. PBODR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port B Input Data Register (PBPIN) Bit 7 6 543210 PB7PIN PB6PIN PB5PIN PB4PIN PB3PIN PB2PIN PB1PIN PB0PIN Initial value —* —* —* —* —* —* —* —* Read/Write R R RRRRRR Note: * Determined by the state of pins PB7 to PB0. Reading PBPIN always returns the pin states. PBPIN has the same address as P8DDR. If a write is performed, data will be written to P8DDR and the port 8 settings will change. |
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