ST7263BEx datasheet(122/186 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7263Bxx

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Doc ID 7516 Rev 8

I²C Clock Control register (CCR)

Reset value: 0000 0000 (00h)

2 ARLO Arbitration lost.

This bit is set by hardware when the interface loses the arbitration of the bus to

another master. An interrupt is generated if ITE=1. It is cleared by software reading

SR2 register or by hardware when the interface is disabled (PE=0).

After an ARLO event the interface switches back automatically to Slave mode

(M/SL=0).

The SCL line is not held low while ARLO=1.

0: No arbitration lost detected

1: Arbitration lost detected

Note: In a Multimaster environment, when the interface is configured in Master

Receive mode it does not perform arbitration during the reception of the

Acknowledge Bit. Mishandling of the ARLO bit from the I2CSR2 register

may occur when a second master simultaneously requests the same data

from the same slave and the I2C master does not acknowledge the data.

The ARLO bit is then left at 0 instead of being set.

1 BERR Bus error.

This bit is set by hardware when the interface detects a misplaced Start or Stop

condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2

The SCL line is not held low while BERR=1.

0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

Note: If a Bus Error occurs, a Stop or a repeated Start condition should be

generated by the Master to re-synchronize communication, get the

transmission acknowledged and the bus released for further communication

0 GCAL General Call (Slave mode).

This bit is set by hardware when a general call address is detected on the bus while

ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when

the interface is disabled (PE=0).

0: No general call address detected on bus

1: general call address detected on bus

FM/SM

CC6

CC5

CC4

CC3

CC2

CC1

CC0

Read/write

7 FM/SM Fast/Standard I²C mode.

This bit is set and cleared by software. It is not cleared when the interface is

disabled (PE=0).

0: Standard I²C mode

1: Fast I²C mode

[6:0] CC[6:0] 7-bit clock divider.

These bits select the speed of the bus (FSCL) depending on the I²C mode. They are

not cleared when the interface is disabled (PE=0).

Refer to the Electrical Characteristics section for the table of value.

Note: The programmed FSCL assumes no load on SCL and SDA lines.

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