ST7263BEx datasheet(118/186 Pages) STMICROELECTRONICS

部件名	ST7263BEx

功能描述	Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI and I²C

PDF	186 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

118 / 186 page

On-chip peripherals

ST7263Bxx

118/186

Doc ID 7516 Rev 8

2 ACK Acknowledge enable.

This bit is set and cleared by software. It is also cleared by hardware when the

interface is disabled (PE=0).

0: No acknowledge returned

1: Acknowledge returned after an address byte or a data byte is received

1 STOP Generation of a Stop condition.

This bit is set and cleared by software. It is also cleared by hardware in master

mode. Note: This bit is not cleared when the interface is disabled (PE=0).

In Master mode:

0: No stop generation

1: Stop generation after the current byte transfer or after the current Start condition

is sent. The STOP bit is cleared by hardware when the Stop condition is sent.

In Slave mode:

0: No stop generation

1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this

mode the STOP bit has to be cleared by software.

0 ITE Interrupt enable.

This bit is set and cleared by software and cleared by hardware when the interface

is disabled (PE=0).

0: Interrupts disabled

1: Interrupts enabled

Refer to Figure 49 for the relationship between the events and the interrupt.

SCL is held low when the SB, BTF or ADSL flags or an EV6 event (See Figure 48)

is detected.

ST7263BEx 数据表(PDF) 118 Page - STMicroelectronics