ST7263BEx datasheet(114/186 Pages) STMICROELECTRONICS

114 / 186 page

On-chip peripherals

ST7263Bxx

114/186

Doc ID 7516 Rev 8

each 9-bit transaction:

Single Master mode

If a Start or Stop is issued during the first or second pulse of a 9-bit transaction, the

BERR flag will not be set and transfer will continue however the BUSY flag will be reset.

To work around this, slave devices should issue a NACK when they receive a

misplaced Start or Stop. The reception of a NACK or BUSY by the master in the middle

of communication gives the possibility to reinitiate transmission.

Multimaster mode

Normally the BERR bit would be set whenever unauthorized transmission takes place

while transfer is already in progress. However, an issue will arise if an external master

generates an unauthorized Start or Stop while the I2C master is on the first or second

pulse of a 9-bit transaction. It is possible to work around this by polling the BUSY bit

during I2C master mode transmission. The resetting of the BUSY bit can then be

handled in a similar manner as the BERR flag being set.

●

AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by

hardware with an interrupt if the ITE bit is set. To resume, set the START or STOP bit.

The AF bit is cleared by reading the I2CSR2 register. However, if read before the

completion of the transmission, the AF flag will be set again, thus possibly generating a

new interrupt. Software must ensure either that the SCL line is back at 0 before reading

the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse

of a transmitted byte.

●

ARLO: Detection of an arbitration lost condition.

In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and

the interface goes automatically back to slave mode (the M/SL bit is cleared).

Note:

In all these cases, the SCL line is not held low; however, the SDA line can remain low if the

last bits transmitted are all 0. While AF=1, the SCL line may be held low due to SB or BTF

flags that are set at the same time. It is then necessary to release both lines by software.

ST7263BEx 数据表(PDF) 114 Page - STMicroelectronics