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ADE7880 数据表(PDF) 37 Page - Analog Devices |
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ADE7880 数据表(HTML) 37 Page - Analog Devices |
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37 / 104 page ![]() Data Sheet ADE7880 Rev. A | Page 37 of 104 Figure 63 illustrates how the phase compensation is used to remove x = −1° phase lead in IA of the current channel from the external current transducer (equivalent of 55.5 μs for 50 Hz systems). To cancel the lead (1°) in the current channel of Phase A, a phase lead must be introduced into the corresponding voltage channel. Using Equation 8, APHCAL is 57 least significant bits, rounded up from 56.8. The phase lead is achieved by introducing a time delay of 55.73 μs into the Phase A current. −6.732° to +1.107° and the resolution is 0.0176° (360° × 50 Hz/ 1.024 MHz). Given a phase error of x degrees, measured using the phase voltage as the reference, the corresponding LSBs are computed dividing x by the phase resolution (0.0211°/LSB for 60 Hz and 0.0176°/LSB for 50 Hz). Results between −383 and +63 only are acceptable; numbers outside this range are not accepted. If the current leads the voltage, the result is negative and the absolute value is written into the PHCAL registers. If the current lags the voltage, the result is positive and 512 is added to the result before writing it into xPHCAL. APHCAL, BPHCAL, or CPHCAL = ⎪ ⎪ ⎭ ⎪ ⎪ ⎬ ⎫ ⎪ ⎪ ⎩ ⎪ ⎪ ⎨ ⎧ > + ≤ 0 , 512 _ 0 , _ x resolution phase x x resolution phase x (9) As stated in the Current Waveform Gain Registers section, the serial ports of the ADE7880 work on 32-, 16-, or 8-bit words. As shown in Figure 62, APHCAL, BPHCAL, and CPHCAL 10-bit registers are accessed as 16-bit registers with the six MSBs padded with 0s. 0000 00 15 10 9 0 xPHCAL Figure 62. xPHCAL Registers Communicated As 16-Bit Registers PHASE CALIBRATION APHCAL = 57 ADC PGA3 VAP VA VN ADC PGA1 IAP IA IAN PHASE COMPENSATION ACHIEVED DELAYING IA BY 56µs 50Hz 1° VA IA VA IA Figure 63. Phase Calibration on Voltage Channels |
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