ADE7880 datasheet(32/104 Pages) AD

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ADE7880

Data Sheet

Rev. A | Page 32 of 104

If Bit 19 (SEQERR) in the MASK1 register is set to 1 and a

phase sequence error event is triggered, the IRQ1 interrupt pin

is driven low. The status bit is cleared and the IRQ1 pin is set

high by writing to the STATUS1 register with the Status Bit 19

(SEQERR) set to 1.

The phase sequence error detection circuit is functional only

when the ADE7880 is connected in a 3-phase, 4-wire, three voltage

sensors configuration (Bits[5:4], CONSEL[1:0] in the ACCMODE

sensors are used; therefore, it is not recommended to use the

detection circuit. In these cases, use the time intervals between

phase voltages to analyze the phase sequence (see the Time

Interval Between Phases section for details).

Figure 52 presents the case in which Phase A voltage is not

followed by Phase B voltage but by Phase C voltage. Every time

a negative-to-positive zero crossing occurs, Bit 19 (SEQERR) in

the STATUS1 register is set to 1 because such zero crossings on

Phase C, Phase B, or Phase A cannot come after zero crossings

from Phase A, Phase C, or respectively, Phase B zero crossings.

ZX B

ZX C

PHASE C

PHASE B

PHASE A

A, B, C PHASE

VOLTAGES AFTER

LPF1

BIT 19 (SEQERR) IN

STATUS1 REGISTER

IRQ1

ZX A

STATUS1[19] SET TO 1

STATUS1[19] CANCELLED

BY A WRITE TO THE

STATUS1 REGISTER WITH

SEQERR BIT SET

Figure 52. SEQERR Bit Set to 1 When Phase A Voltage Is Followed by

Phase C Voltage

Once a phase sequence error has been detected, the time

measurement between various phase voltages (see the Time

Interval Between Phases section) can help to identify which

phase voltage should be considered with another phase current

in the computational data path. Bits[9:8] (VTOIA[1:0]),

Bits[11:10] (VTOIB[1:0]), and Bits[13:12] (VTOIC[1:0]) in the

CONFIG register can be used to direct one phase voltage to the

data path of another phase. See the Changing Phase Voltage

Data path section for details.

Time Interval Between Phases

The ADE7880 has the capability to measure the time delay

between phase voltages, between phase currents, or between

voltages and currents of the same phase. The negative-to-positive

transitions identified by the zero-crossing detection circuit are

used as start and stop measuring points. Only one set of such

measurements is available at one time, based on Bits[10:9]

(ANGLESEL[1:0]) in the COMPMODE register.

ZX C

ZX B

PHASE B

PHASE C

PHASE A

ZX A

Figure 53. Regular Succession of Phase A, Phase B, and Phase C

When the ANGLESEL[1:0] bits are set to 00, the default value,

the delays between voltages and currents on the same phase are

measured. The delay between Phase A voltage and Phase A

current is stored in the 16-bit unsigned ANGLE0 register (see

Figure 54 for details). In a similar way, the delays between

voltages and currents on Phase B and Phase C are stored in the

ANGLE1 and ANGLE2 registers, respectively.

PHASE A

CURRENT

ANGLE0

PHASE A

VOLTAGE

Figure 54. Delay Between Phase A Voltage and Phase A Current Is

Stored in the ANGLE0 Register

When the ANGLESEL[1:0] bits are set to 01, the delays between

phase voltages are measured. The delay between Phase A

voltage and Phase C voltage is stored into the ANGLE0 register.

The delay between Phase B voltage and Phase C voltage is

stored in the ANGLE1 register, and the delay between Phase A

voltage and Phase B voltage is stored in the ANGLE2 register

(see Figure 55 for details).

When the ANGLESEL[1:0] bits are set to 10, the delays between

phase currents are measured. Similar to delays between phase

voltages, the delay between Phase A and Phase C currents is

stored into the ANGLE0 register, the delay between Phase B and

Phase C currents is stored in the ANGLE1 register, and the

delay between Phase A and Phase B currents is stored into the

ANGLE2 register (see Figure 55 for details).

PHASE B

PHASE C

PHASE A

ANGLE2

ANGLE0

ANGLE1

Figure 55. Delays Between Phase Voltages (Currents)

The ANGLE0, ANGLE1, and ANGLE2 registers are 16-bit

unsigned registers with 1 LSB corresponding to 3.90625 μs

(256 kHz clock), which means a resolution of 0.0703° (360° ×

50 Hz/256 kHz) for 50 Hz systems and 0.0843° (360° × 60 Hz/

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