ADE7880 datasheet(45/104 Pages) AD

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Data Sheet

ADE7880

Rev. A | Page 45 of 104

Fundamental Active Power Calculation

The ADE7880 computes the fundamental active power using

a proprietary algorithm that requires some initializations function

of the frequency of the network and its nominal voltage measured

in the voltage channel. Bit 14 (SELFREQ) in the COMPMODE

which the ADE7880 is connected. If the network frequency is

50 Hz, clear this bit to 0 (the default value). If the network fre-

quency is 60 Hz, set this bit to 1. In addition, initialize the VLEVEL

24-bit signed register with a positive value based on the

following equation:

VLEVEL

(22)

where:

UFS is the rms value of the phase voltages when the ADC inputs

are at full scale.

Un is the rms nominal value of the phase voltage.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words

and the DSP works on 28 bits. Similar to the registers presented

in Figure 43, the VLEVEL 24-bit signed register is accessed as a

32-bit register with four most significant bits padded with 0s

and sign extended to 28 bits.

Table 13 presents the settling time for the fundamental active

power measurement.

Table 13. Settling Time for Fundamental Active Power

Input Signals

63% PMAX

100% PMAX

375 ms

875 ms

Active Power Gain Calibration

Note that the average active power result from the LPF2 output

in each phase can be scaled by ±100% by writing to the phase’s

watt gain 24-bit register (APGAIN, BPGAIN, CPGAIN). The

xPGAIN registers are placed on data paths of all powers

computed by the ADE7880: total active powers, fundamental

active and reactive powers and apparent powers. This is possible

because all power data paths have identical overall gains.

Therefore, to compensate the gain errors in various powers data

paths it is sufficient to analyze only one power data path, for

example the total active power, calculate the correspondent

APGAIN, BPGAIN and CPGAIN registers and all the power

data paths are gain compensated.

The power gain registers are twos complement, signed registers

and have a resolution of 2−23/LSB. Equation 23 describes

mathematically the function of the power gain registers.

⎟

⎠

⎞

⎜

⎝

⎛ +

gister

Gain

Power

Output

LPF

Data

Power

Average

(23)

The output is scaled by −50% by writing 0xC00000 to the watt

gain registers, and it is increased by +50% by writing 0x400000

to them. These registers are used to calibrate the active, reactive

and apparent power (or energy) calculation for each phase.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words,

and the DSP works on 28 bits. Similar to registers presented in

Figure 43, the APGAIN, BPGAIN, and CPGAIN 24-bit signed

registers are accessed as 32-bit registers with the four MSBs

padded with 0s and sign extended to 28 bits.

Active Power Offset Calibration

The ADE7880 incorporates a watt offset 24-bit register on each

phase and on each active power. The AWATTOS, BWATTOS,

and CWATTOS registers compensate the offsets in the total

active power calculations, and the AFWATTOS, BFWATTOS,

and CFWATTOS registers compensate offsets in the fundamental

active power calculations. These are signed twos complement,

24-bit registers that are used to remove offsets in the active

power calculations. An offset can exist in the power calculation

due to crosstalk between channels on the PCB or in the chip

itself. One LSB in the active power offset register is equivalent

to 1 LSB in the active power multiplier output. With full-scale

current and voltage inputs, the LPF2 output is PMAX =

27,059,678. At −80 dB down from the full scale (active power

scaled down 104 times), one LSB of the active power offset

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words

and the DSP works on 28 bits. Similar to registers presented in

Figure 43, the AWATTOS, BWATTOS, CWATTOS, AFWATTOS,

BFWATTOS, and CFWATTOS 24-bit signed registers are

accessed as 32-bit registers with the four MSBs padded with

0s and sign extended to 28 bits.

Sign of Active Power Calculation

The average active power is a signed calculation. If the phase

difference between the current and voltage waveform is

more than 90°, the average power becomes negative. Negative

power indicates that energy is being injected back on the grid.

The ADE7880 has sign detection circuitry for active power

calculations. It can monitor the total active powers or the

fundamental active powers. As described in the Active Energy

Calculation section, the active energy accumulation is performed

in two stages. Every time a sign change is detected in the energy

accumulation at the end of the first stage, that is, after the energy

accumulated into the internal accumulator reaches the WTHR

each phase active power can be read in the PHSIGN register.

Bit 6 (REVAPSEL) in the ACCMODE register sets the type of

active power being monitored. When REVAPSEL is 0, the

default value, the total active power is monitored. When

REVAPSEL is 1, the fundamental active power is monitored.

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