ADE7880 datasheet(70/104 Pages) AD

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ADE7880

Data Sheet

Rev. A | Page 70 of 104

The VANOLOAD register usually contains the same value

as the APNOLOAD register. When APNOLOAD and

VANOLOAD are set to 0x0, the no load detection circuit

is disabled. If only VANOLOAD is set to 0, then the no load

condition is triggered based only on the total active power

being lower than APNOLOAD. In the same way, if only

APNOLOAD is set to 0x0, the no load condition is triggered

based only on the apparent power being lower than VANOLOAD.

Bit 0 (NLOAD) in the STATUS1 register is set when a no load

condition in one of the three phases is triggered. Bits[2:0]

(NLPHASE[2:0]) in the PHNOLOAD register indicate the state

of all phases relative to a no load condition and are set simulta-

neously with Bit NLOAD in the STATUS1 register. NLPHASE[0]

indicates the state of Phase A, NLPHASE[1] indicates the state

of Phase B, and NLPHASE[2] indicates the state of Phase C.

When Bit NLPHASE[x] is cleared to 0, it means the phase is out

of a no load condition. When set to 1, it means the phase is in a

no load condition.

An interrupt attached to Bit 0 (NLOAD) in the STATUS1

If enabled, the IRQ1 pin is set to low, and the status bit is set

to 1 whenever one of three phases enters or exits this no load

condition. To find the phase that triggered the interrupt, the

PHNOLOAD register is read immediately after reading the

STATUS1 register. Next, the status bit is cleared, and the IRQ1

pin is set to high by writing to the STATUS1 register with the

corresponding bit set to 1.

No Load Detection Based on Fundamental Active and

Reactive Powers

This no load condition is triggered when no less significant bits

are accumulated into the fundamental active and reactive energy

registers on one phase (xFWATTHR and xFVARHR, x = A, B,

or C) for a time indicated in the respective APNOLOAD and

VARNOLOAD unsigned 16-bit registers. In this case, the

fundamental active and reactive energies of that phase are not

accumulated and no CFx pulses are generated based on these

energies. APNOLOAD is the same no load threshold set for

the total active powers. The VARNOLOAD register usually

contains the same value as the APNOLOAD register. If only

APNOLOAD is set to 0x0, then the fundamental active power

is accumulated without restriction. In the same way, if only

VARNOLOAD is set to 0x0, the fundamental reactive power is

accumulated without restriction.

Bit 1 (FNLOAD) in the STATUS1 register is set when this no

load condition in one of the three phases is triggered. Bits[5:3]

(FNLPHASE[2:0]) in the PHNOLOAD register indicate the

state of all phases relative to a no load condition and are set

simultaneously with Bit FNLOAD in the STATUS1 register.

FNLPHASE[0] indicates the state of Phase A, FNLPHASE[1]

indicates the state of Phase B, and FNLPHASE[2] indicates the

state of Phase C. When Bit FNLPHASE[x] is cleared to 0, it

means the phase is out of the no load condition. When set to 1,

it means the phase is in a no load condition.

An interrupt attached to the Bit 1 (FNLOAD) in the STATUS1

enabled, the IRQ1 pin is set low and the status bit is set to 1

whenever one of three phases enters or exits this no load

condition. To find the phase that triggered the interrupt, the

PHNOLOAD register is read immediately after reading the

STATUS1 register. Then the status bit is cleared and the IRQ1

pin is set back high by writing to the STATUS1 register with the

corresponding bit set to 1.

No Load Detection Based on Apparent Power

This no load condition is triggered when no less significant bits

are accumulated into the apparent energy register on one phase

(xVAHR, x = A, B, or C) for a time indicated by the VANOLOAD

unsigned 16-bit register. In this case, the apparent energy of that

phase is not accumulated and no CFx pulses are generated based

on this energy.

The equation used to compute the VANOLOAD unsigned

16-bit value is

PMAX

VATHR

VANOLOAD

−

(51)

where:

Y is the required no load current threshold computed relative to

full scale. For example, if the no load threshold current is set

10,000 times lower than full scale value, then Y=10,000.

VATHR is the VATHR register used as the threshold of the first

stage energy accumulator (see Apparent Energy Calculation

section) PMAX = 27,059,678 = 0x19CE5DE, the instantaneous

apparent power computed when the ADC inputs are at full

scale. When the VANOLOAD register is set to 0x0, the no load

detection circuit is disabled.

Bit 2 (VANLOAD) in the STATUS1 register is set when this no

load condition in one of the three phases is triggered. Bits[8:6]

(VANLPHASE[2:0]) in the PHNOLOAD register indicate the

state of all phases relative to a no load condition and they are set

simultaneously with Bit VANLOAD in the STATUS1 register:

•

Bit VANLPHASE[0] indicates the state of Phase A.

•

Bit VANLPHASE[1] indicates the state of Phase B.

•

Bit VANLPHASE[2] indicates the state of Phase C.

When Bit VANLPHASE[x] is cleared to 0, it means the phase is

out of no load condition. When set to 1, it means the phase is in

no load condition.

An interrupt attached to Bit 2 (VANLOAD) in the STATUS1

enabled, the IRQ1 pin is set low and the status bit is set to 1

whenever one of three phases enters or exits this no load

condition. To find the phase that triggered the interrupt, the

PHNOLOAD register is read immediately after reading the

STATUS1 register. Next, the status bit is cleared, and the IRQ1

pin is set to high by writing to the STATUS1 register with the

corresponding bit set to 1.

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