ADE7880 datasheet(77/104 Pages) AD

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Data Sheet

ADE7880

Rev. A | Page 77 of 104

15 14

SCLK

MOSI

MISO

31 30

1 0

000

Figure 104. SPI Read Operation of a 32-Bit Register

SCLK

MOSI

MISO

0001

ADDRESS

VALUE

Figure 105. SPI Read Operation of n 32-Bit Harmonic Calculations Registers

SPI Read Operation of Harmonic Calculations Registers

The registers containing the harmonic calculation results are

located starting at Address 0xE880 and are all 32-bit width.

They can be read in two ways: one register at a time (see the SPI

Read Operation section for details) or multiple consecutive

registers at a time in a burst mode. The burst mode initiates

when the master sets the SS/HSA pin low and begins sending

one byte, representing the address of the

, on the

MOSI line. The address is the same address byte used for

reading only one register. The master sets data on the MOSI line

starting with the first high-to-low transition of SCLK. The SPI

of the

samples data on the low-to-high transitions of

SCLK. Next, the master sends the 16-bit address of the first

harmonic calculations register that is read. After the

receives the last bit of the address of the register on a low-to-

high transition of SCLK, it begins to transmit its contents on the

MISO line when the next SCLK high-to-low transition occurs;

thus, the master can sample the data on a low-to-high SCLK

transition. After the master receives the last bit of the first

sends the harmonic calculations register

placed at the next location and so forth until the master sets the

ADE7880

SS and SCLK lines high and the communication ends. The data

lines, MOSI and MISO, go into a high impedance state. See

for details of the SPI read operation of harmonic

calculations registers.

Figure 105

SPI Write Operation

The write operation using the SPI interface of the ADE7880

initiates when the master sets the SS/HSA pin low and begins

sending one byte representing the address of the

the MOSI line. The master sets data on the MOSI line starting

with the first high-to-low transition of SCLK. The SPI of the

samples data on the low-to-high transitions of SCLK.

The most significant seven bits of the address byte can have any

value, but as a good programming practice, they should be

different from 0111000b, the seven bits used in the I2C protocol.

Bit 0 (read/

ADE7880

write) of the address byte must be 0 for a write

operation. Next, the master sends both the 16-bit address of the

transmitted, the master sets the SS and SCLK lines high at the

end of the SCLK cycle and the communication ends. The data

lines, MOSI and MISO, go into a high impedance state. See

for details of the SPI write operation.

Figure 106

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