ADE7880 datasheet(24/104 Pages) AD

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ADE7880

Data Sheet

Rev. A | Page 24 of 104

HARDWARE RESET

The ADE7880 has a RESET pin. If the

is in PSM0

mode and the

ADE7880

RESET pin is set low, then the

enters

the hardware reset state. The

must be in PSM0 mode

for a hardware reset to be considered. Setting the

ADE7880

RESET pin

low while the

is in PSM1, PSM2, and PSM3 modes

does not have any effect.

ADE7880

If the ADE7880 is in PSM0 mode and the RESET pin is toggled

from high to low and then back to high after at least 10 μs, all the

registers are set to their default values, including the CONFIG2 and

LPOILVL registers. The

signals the end of the transition

period by triggering the

ADE7880

IRQ1 interrupt pin low and setting Bit 15

(RSTDONE) in the STATUS1 register to 1. This bit is 0 during

the transition period and becomes 1 when the transition ends.

The status bit is cleared and the IRQ1 pin is returned high by

writing to the STATUS1 register with the corresponding bit set

to 1.

After a hardware reset, the DSP is in idle mode, which means it

does not execute any instruction.

Because the I2C port is the default serial port of the ADE7880, it

becomes active after a reset state. If SPI is the port used by the

external microprocessor, the procedure to enable it must be

repeated immediately after the RESET pin is toggled back to

high (see the

section for details).

Serial Interfaces

At this point, it is recommended to initialize all of the ADE7880

registers and then write 0x0001 into the Run register to start the

DSP. See the Digital Signal Processor section for details on the

Run register.

SOFTWARE RESET FUNCTIONALITY

Bit 7 (SWRST) in the CONFIG register manages the software

reset functionality in PSM0 mode. The default value of this bit is 0.

If this bit is set to 1, then the ADE7880 enters the software reset

state. In this state, almost all internal registers are set to their

default values. In addition, the choice of which serial port, I2C or

SPI, is in use remains unchanged if the lock-in procedure has

been executed previously (see the Serial Interfaces section for

details). The registers that maintain their values despite the

SWRST bit being set to 1 are the CONFIG2 and LPOILVL

registers. When the software reset ends, Bit 7 (SWRST) in the

CONFIG register is cleared to 0, the IRQ1 interrupt pin is set

low, and Bit 15 (RSTDONE) in the STATUS1 register is set to 1.

This bit is 0 during the transition period and becomes 1 when

the transition ends. The status bit is cleared and the IRQ1 pin is

set back high by writing to the STATUS1 register with the

corresponding bit set to 1.

After a software reset ends, the DSP is in idle mode, which

means it does not execute any instruction. As a good programming

practice, it is recommended to initialize all the ADE7880 registers

and then write 0x0001 into the Run register to start the DSP

(see the Digital Signal Processor section for details on the Run

Software reset functionality is not available in PSM1, PSM2, or

PSM3 mode.

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