ADE7880 datasheet(27/104 Pages) AD

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Data Sheet

ADE7880

Rev. A | Page 27 of 104

AIGAIN[23:0]

DSP

REFERENCE

HPFEN BIT

CONFIG3[0]

DIGITAL

INTEGRATOR

INTEN BIT

CONFIG[0]

TOTAL/FUNDAMENTAL

ACTIVE AND REACTIVE

POWER CALCULATION

CURRENT PEAK,

OVERCURRENT

DETECT

IAWV WAVEFORM

SAMPLE REGISTER

CURRENT RMS (IRMS)

CALCULATION

HPF

ADC

PGA1

IAP

ZX DETECTION

PGA1 BITS

GAIN[2:0]

×1, ×2, ×4, ×8, ×16

VIN

IAN

ANALOG INPUT RANGE

ANALOG OUTPUT RANGE

0x514791 =

+5,326,737

ZX SIGNAL

DATA RANGE

0xAEB86F =

–5,326,737

0x5A7540 =

+5,928,256

CURRENT CHANNEL

DATA RANGE AFTER

INTEGRATION

0xA58AC0 =

–5,928,256

0x514791 =

+5,326,737

CURRENT CHANNEL

DATA RANGE

0xAEB86F =

–5,326,737

+0.5V/GAIN

–0.5V/GAIN

LPF1

Figure 41. Current Channel Signal Path

NIGAIN[23:0]

DSP

REFERENCE

HPFEN BIT

CONFIG3[0]

DIGITAL

INTEGRATOR

ININTEN BIT

CONFIG3[3]

INWV WAVEFORM

SAMPLE REGISTER

CURRENT RMS (IRMS)

CALCULATION

HPF

ADC

PGA2

IAP

PGA2 BITS

GAIN[5:3]

×1, ×2, ×4, ×8, ×16

VIN

IAN

Figure 42. Neutral Current Signal Path

Current Waveform Gain Registers

There is a multiplier in the signal path of each phase and

neutral current. The current waveform can be changed by

±100% by writing a corresponding twos complement number to

the 24-bit signed current waveform gain registers (AIGAIN,

BIGAIN, CIGAIN, and NIGAIN). For example, if 0x400000 is

written to those registers, the ADC output is scaled up by 50%.

To scale the input by −50%, write 0xC00000 to the registers.

Equation 4 describes mathematically the function of the current

waveform gain registers.

Current Waveform =

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

Gain

Current

Content

Output

ADC

(4)

Changing the content of the AIGAIN, BIGAIN, CIGAIN, or

INGAIN registers affects all calculations based on its current;

that is, it affects the corresponding phase active/reactive/

apparent energy and current rms calculation. In addition,

waveform samples scale accordingly.

Note that the serial ports of the ADE7880 work on 32-, 16-, or

8-bit words, and the DSP works on 28 bits. The 24-bit AIGAIN,

BIGAIN, CIGAIN, and NIGAIN registers are accessed as 32-bit

registers with the four most significant bits (MSBs) padded with

0s and sign extended to 28 bits. See Figure 43 for details.

28 27

24 23

24-BIT NUMBER

0000

BITS[27:24] ARE

EQUAL TO BIT 23

BIT 23 IS A SIGN BIT

Figure 43. 24-Bit xIGAIN Transmitted as 32-Bit Words

Current Channel HPF

The ADC outputs can contain a dc offset. This offset can create

errors in power and rms calculations. High-pass filters (HPFs)

are placed in the signal path of the phase and neutral currents

and of the phase voltages. If enabled, the HPF eliminates any dc

offset on the current channel. All filters are implemented in the

DSP and, by default, they are all enabled: Bit 0 (HPFEN) of the

CONFIG3[7:0] register is set to 1. All filters are disabled by

setting Bit 0 (HPFEN) to 0.

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