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ADE7880 数据表(PDF) 92 Page - Analog Devices

部件名 ADE7880
功能描述  Polyphase Multifunction Energy Metering IC
PDF  104 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7880 数据表(HTML) 92 Page - Analog Devices

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ADE7880
Data Sheet
Rev. A| Page 92 of 104
Bit
Mnemonic
Default Value
Description
24
PKV
0
When this bit is set to 1, it indicates that the period used to detect the peak value in
the voltage channel has ended. VPEAK register contains the peak value and the
phase where the peak has been detected (see Table 35).
25
CRC
0
When this bit is set to 1, it indicates the ADE7880 has computed a different
checksum relative to the one computed when the Run register was set to 1.
31:26
Reserved
000 0000
Reserved. These bits are always 0.
Table 38. MASK0 Register (Address 0xE50A)
Bit
Mnemonic
Default Value
Description
0
AEHF
0
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total
active energy registers (AWATTHR, BWATTHR, or CWATTHR) changes.
1
FAEHF
0
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the
fundamental active energy registers (AFWATTHR, BFWATTHR, or CFWATTHR)
changes.
2
Reserved
0
This bit does not manage any functionality.
3
FREHF
0
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the
fundamental reactive energy registers (AFVARHR, BFVARHR, or CFVARHR) changes.
4
VAEHF
0
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the
apparent energy registers (AVAHR, BVAHR, or CVAHR) changes.
5
LENERGY
0
When this bit is set to 1, in line energy accumulation mode, it enables an interrupt at
the end of an integration over an integer number of half line cycles set in the
LINECYC register.
6
REVAPA
0
When this bit is set to 1, it enables an interrupt when the Phase A active power
identified by Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental)
changes sign.
7
REVAPB
0
When this bit is set to 1, it enables an interrupt when the Phase B active power
identified by Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental)
changes sign.
8
REVAPC
0
When this bit is set to 1, it enables an interrupt when the Phase C active power
identified by Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental)
changes sign.
9
REVPSUM1
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in
the CF1 data path changes sign.
10
REVFRPA
0
When this bit is set to 1, it enables an interrupt when the Phase A fundamental
reactive power changes sign.
11
REVFRPB
0
When this bit is set to 1, it enables an interrupt when the Phase B fundamental
reactive power changes sign.
12
REVFRPC
0
When this bit is set to 1, it enables an interrupt when the Phase C fundamental
reactive power changes sign.
13
REVPSUM2
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in
the CF2 data path changes sign.
14
CF1
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs
at the CF1 pin, that is an active low pulse is generated. The interrupt can be enabled
even if the CF1 output is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE
register. The type of power used at the CF1 pin is determined by Bits[2:0]
(CF1SEL[2:0]) in the CFMODE register (see Table 44).
15
CF2
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs
at CF2 pin, that is an active low pulse is generated. The interrupt may be enabled
even if the CF2 output is disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE
register. The type of power used at the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0])
in the CFMODE register (see Table 44).
16
CF3
When this bit is set to 1, it enables an interrupt when a high to low transition occurs
at CF3 pin, that is an active low pulse is generated. The interrupt may be enabled
even if the CF3 output is disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE
register. The type of power used at the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0])
in the CFMODE register (see Table 44).
17
DREADY
0
When this bit is set to 1, it enables an interrupt when all periodical (at 8 kHz rate)
DSP computations finish.



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