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ADE7880 数据表(PDF) 52 Page - Analog Devices |
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ADE7880 数据表(HTML) 52 Page - Analog Devices |
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52 / 104 page  ADE7880 Data Sheet Rev. A | Page 52 of 104 On the ADE7880, the fundamental phase reactive powers are accumulated in the AFVARHR, BFVARHR, and CFVARHR 32- bit signed registers. The reactive energy register content can roll over to full-scale negative (0x80000000) and continue increasing in value when the reactive power is positive. Conversely, if the reactive power is negative, the energy register underflows to full-scale positive (0x7FFFFFFF) and continues to decrease in value. The ADE7880 provides a status flag to signal when one of the xFVARHR registers is half full. Bit 3 (FREHF) in the STATUS0 register is set when Bit 30 of one of the xFVARHR registers changes, signifying one of these registers is half full. If the reactive power is positive, the var-hour register becomes half full when it increments from 0x3FFF FFFF to 0x4000 0000. If the reactive power is negative, the var-hour register becomes half full when it decrements from 0xC000 0000 to 0xBFFF FFFF. Setting Bit3 in the MASK0 register enables the FREHF interrupt. If enabled, the IRQ0 pin is set low and the status bit is set to 1 whenever one of the energy registers, xFVARHR, becomes half full. The status bit is cleared and the IRQ0 pin is set to high by writing to the STATUS0 register with the corresponding bit set to 1. Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a read-with-reset for all var-hour accumulation registers, that is, the registers are reset to 0 after a read operation. Integration Time Under Steady Load The discrete time sample period (T) for the accumulation register is 976.5625 ns (1.024 MHz frequency). With full-scale sinusoidal signals on the analog inputs and a 90° phase difference between the voltage and the current signal (the largest possible reactive power), the average word value representing the reactive power is PMAX = 27,059,678 = 0x19CE5DE. If the VARTHR threshold is set at 3, its minimum recommended value, the first stage accumulator generates a pulse that is added to var-hour registers every sec 531 . 14 10 024 . 1 2 3 6 27 μ = × × × PMAX The maximum value that can be stored in the var-hour accumulation register before it overflows is 231 − 1 or 0x7FFFFFFF. The integration time is calculated as Time = 0x7FFF,FFFF × 14.531 μs = 8 hr 40 min 6 sec (39) Energy Accumulation Modes The fundamental reactive power accumulated in each var-hour accumulation 32-bit register (AFVARHR, BFVARHR, and CFVARHR) depends on the configuration of Bits[5:4] (CONSEL[1:0]) in the ACCMODE register, in correlation with the watt-hour registers. The different configurations are described in Table 18. Note that IA’/IB’/IC’ are the phase- shifted current waveforms. Table 18. Inputs to Var-Hour Accumulation Registers CONSEL[1:0] AFVARHR BFVARHR CFVARHR 00 VA × IA’ VB × IB’ VC × IC’ 01 VA × IA’ VB × IB’ VB = VA − VC1 VC × IC’ 10 VA × IA’ VB × IB’ VC x IC’ VB = −VA − VC 11 VA × IA’ VB × IB’ VC × IC’ VB = −VA 1 In a 3-phase three wire case (CONSEL[1:0] = 01), the ADE7880 computes the rms value of the line voltage between phases A and C and stores the result into BVRMS register (see the Voltage RMS in 3-Phase Three Wire Delta Configurations section). Consequently, the ADE7880 computes powers associated with Phase B that do not have physical meaning. To avoid any errors in the frequency output pins (CF1, CF2, or CF3) related to the powers associated with Phase B, disable the contribution of Phase B to the energy to frequency converters by setting bits TERMSEL1[1] or TERMSEL2[1] or TERMSEL3[1] to 0 in COMPMODE register (see the Energy-to-Frequency Conversion section). Bits[3:2] (VARACC[1:0]) in the ACCMODE register determine how the reactive power is accumulated in the var-hour registers and how the CF frequency output can be generated function of total and fundamental active and reactive powers. See the Energy- to-Frequency Conversion section for details. Line Cycle Reactive Energy Accumulation Mode As mentioned in the Line Cycle Active Energy Accumulation Mode section, in line cycle energy accumulation mode, the energy accumulation can be synchronized to the voltage channel zero crossings so that reactive energy can be accumulated over an integral number of half line cycles. In this mode, the ADE7880 transfers the reactive energy accumulated in the 32-bit internal accumulation registers into the xFVARHR registers after an integral number of line cycles, as shown in Figure 78. The number of half line cycles is specified in the LINECYC register. The line cycle reactive energy accumulation mode is activated by setting Bit 1 (LVAR) in the LCYCMODE register. The fundamental reactive energy accumulated over an integer number of half line cycles or zero crossings is available in the var- hour accumulation registers after the number of zero crossings specified in the LINECYC register is detected. When using the line cycle accumulation mode, Bit 6 (RSTREAD) of the LCYCMODE register should be set to Logic 0 because a read with the reset of var-hour registers is not available in this mode. |
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