ADE7880 datasheet(100/104 Pages) AD

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ADE7880

Data Sheet

Rev. A| Page 100 of 104

Bit

Mnemonic

Default Value

Description

REVAPSEL

0: The total active power on each phase is used to trigger a bit in the STATUS0 register as

follows: on Phase A triggers Bit 6 (REVAPA), on Phase B triggers Bit 7 (REVAPB), and on

Phase C triggers Bit 8 (REVAPC).

1: The fundamental active power on each phase is used to trigger a bit in the STATUS0

and on Phase C triggers Bit 8 (REVAPC).

Reserved

Reserved. This bit does not manage any functionality.

Table 50. CONSEL[1:0] Bits in Energy Registers1

Energy Registers

CONSEL[1:0] = 00

CONSEL[1:0] = 01

CONSEL[1:0] = 10

CONSEL[1:0] = 11

AWATTHR, AFWATTHR

VA × IA

BWATTHR, BFWATTHR

VB × IB

VB = VA – VC

VB = −VA – VC

VB = −VA

VB ×IB1

VB × IB

CWATTHR, CFWATTHR

VC × IC

AVARHR, AFVARHR

VA × IA’

BVARHR, BFVARHR

VB × IB’

VB = VA – VC

VB = −VA – VC

VB = −VA

VB × IB’1

VB × IB’

CVARHR, CFVARHR

VC ×IC’

VC × IC’

AVAHR

VA rms × IA rms

BVAHR

VB rms × IB rms

VB = VA – VC1

CVAHR

VC rms × IC rms

1 In a 3-phase three wire case (CONSEL[1:0] = 01), the ADE7880 computes the rms value of the line voltage between Phase A and and Phase C and stores the result into

BVRMS register (see the Voltage RMS in 3-Phase Three Wire Delta Configurations section). Consequently, the ADE7880 computes powers associated with Phase B that

do not have physical meaning. To avoid any errors in the frequency output pins CF1, CF2 or CF3 related to the powers associated with Phase B, disable the

contribution of Phase B to the energy to frequency converters by setting bits TERMSEL1[1], or TERMSEL2[1], or TERMSEL3[1] to 0 in the COMPMODE register (see the

Energy-to-Frequency Conversion section).

Table 51. LCYCMODE Register (Address 0xE702)

Bit

Mnemonic

Default Value

Description

LWATT

0: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,

BFWATTHR, and CFWATTHR) are placed in regular accumulation mode.

1: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,

BFWATTHR, and CFWATTHR) are placed into line cycle accumulation mode.

LVAR

0: the var-hour accumulation registers (AFVARHR, BFVARHR, and CFVARHR) are placed in regular

accumulation mode.

1: the var-hour accumulation registers (AFVARHR, BFVARHR, and CFVARHR) are placed into line-

cycle accumulation mode.

LVA

0: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are placed in regular

accumulation mode.

1: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are placed into line-cycle

accumulation mode.

ZXSEL[0]

0: Phase A is not selected for zero-crossings counts in the line cycle accumulation mode.

1: Phase A is selected for zero-crossings counts in the line cycle accumulation mode. If more

than one phase is selected for zero-crossing detection, the accumulation time is shortened

accordingly.

ZXSEL[1]

0: Phase B is not selected for zero-crossings counts in the line cycle accumulation mode.

1: Phase B is selected for zero-crossings counts in the line cycle accumulation mode.

ZXSEL[2]

0: Phase C is not selected for zero-crossings counts in the line cycle accumulation mode.

1: Phase C is selected for zero-crossings counts in the line cycle accumulation mode.

RSTREAD

0: read-with-reset of all energy registers is disabled. Clear this bit to 0 when Bits[2:0] (LWATT,

LVAR, and LVA) are set to 1.

1: enables read-with-reset of all xWATTHR, xVARHR, xVAHR, xFWATTHR, and xFVARHR registers.

This means a read of those registers resets them to 0.

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