ADE7880 datasheet(12/104 Pages) AD

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ADE7880

Data Sheet

Rev. A | Page 12 of 104

Pin No.

Mnemonic

Description

18, 19, 22, 23

VN, VCP, VBP, VAP

Analog Inputs for the Voltage Channel. This channel is used with the voltage transducer and is

referenced as the voltage channel in this data sheet. These inputs are single-ended voltage inputs

with a maximum signal level of ±0.5 V with respect to VN for specified operation. This channel also

has an internal PGA.

AVDD

This pin provides access to the on-chip 2.5 V analog low dropout regulator (LDO). Do not connect

external active circuitry to this pin. Decouple this pin with a 4.7 μF capacitor in parallel with a

ceramic 220 nF capacitor.

AGND

Ground Reference. This pin provides the ground reference for the analog circuitry. Tie this pin to the

analog ground plane or to the quietest ground reference in the system. Use this quiet ground

reference for all analog circuitry, for example, antialiasing filters, current, and voltage transducers.

VDD

Supply Voltage. This pin provides the supply voltage. In PSM0 (normal power mode), maintain the

supply voltage at 3.3 V ± 10% for specified operation. In PSM1 (reduced power mode), PSM2 (low

power mode), and PSM3 (sleep mode), when the ADE7880 is supplied from a battery, maintain the

supply voltage between 2.4 V and 3.7 V. Decouple this pin to DGND with a 10 μF capacitor in parallel with

a ceramic 100 nF capacitor.

CLKIN

Master Clock. An external clock can be provided at this logic input. Alternatively, a parallel resonant

AT-cut crystal can be connected across CLKIN and CLKOUT to provide a clock source for the

ADE7880. The clock frequency for specified operation is 16.384 MHz. Use ceramic load capacitors of

a few tens of picofarad with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet

for load capacitance requirements.

CLKOUT

A crystal can be connected across this pin and CLKIN (as previously described with Pin 27 in this

table) to provide a clock source for the ADE7880.

29, 32

IRQ0, IRQ1

Interrupt Request Outputs. These are active low logic outputs. See the Interrupts section for a

detailed presentation of the events that can trigger interrupts.

33, 34, 35

CF1, CF2/HREADY,

CF3/HSCLK

Calibration Frequency (CF) Logic Outputs. These outputs provide power information based on the

CF1SEL[2:0], CF2SEL[2:0], and CF3SEL[2:0] bits in the CFMODE register. These outputs are used for

operational and calibration purposes. The full-scale output frequency can be scaled by writing to the

CF1DEN, CF2DEN, and CF3DEN registers, respectively (see the Energy-to-Frequency Conversion

section). CF2 is multiplexed with the HREADY signal generated by the harmonic calculations block.

CF3 is multiplexed with the serial clock output of the HSDC port.

SCLK/SCL

Serial Clock Input for SPI Port/Serial Clock Input for I2C Port. All serial data transfers are synchronized

to this clock (see the Serial Interfaces section). This pin has a Schmidt trigger input for use with a

clock source that has a slow edge transition time, for example, opto-isolator outputs.

MISO/HSD

Data Out for SPI Port/Data Out for HSDC Port.

MOSI/SDA

Data In for SPI Port/Data Out for I2C Port.

SS/HSA

Slave Select for SPI Port/HSDC Port Active.

Exposed Pad

Create a similar pad on the PCB under the exposed pad. Solder the exposed pad to the pad on the

PCB to confer mechanical strength to the package. Do not connect the pads to AGND or DGND.

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