ADE7880 datasheet(99/104 Pages) AD

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Data Sheet

ADE7880

Rev. A| Page 99 of 104

Bit

Mnemonic

Default Value

Description

These bits decide what phase voltage is considered together with Phase C current in the

power path.

00 = Phase C voltage.

01 = Phase A voltage.

10 = Phase B voltage.

13:12

VTOIC[1:0]

11 = reserved. When set, the ADE7880 behaves like VTOIC[1:0] = 00.

15:14

Reserved

Reserved.

Table 48. MMODE Register (Address 0xE700)

Bit

Mnemonic

Default Value

Description

1:0

Reserved

Reserved.

PEAKSEL[0]

PEAKSEL[2:0] bits can all be set to 1 simultaneously to allow peak detection on all three

phases simultaneously. If more than one PEAKSEL[2:0] bits are set to 1, then the peak

measurement period indicated in the PEAKCYC register decreases accordingly because zero

crossings are detected on more than one phase.

When this bit is set to 1, Phase A is selected for the voltage and current peak registers.

PEAKSEL[1]

When this bit is set to 1, Phase B is selected for the voltage and current peak registers.

PEAKSEL[2]

When this bit is set to 1, Phase C is selected for the voltage and current peak registers.

7:5

Reserved

000

Reserved. These bits do not manage any functionality.

Table 49. ACCMODE Register (Address 0xE701)

Bit

Mnemonic

Default Value

Description

00: signed accumulation mode of the total and fundamental active powers. The total and

fundamental active energy registers and the CFx pulses are generated in the same way.

01: positive only accumulation mode of the total and fundamental active powers. In this

mode, although the total and fundamental active energy registers are accumulated in

positive only mode, the CFx pulses are generated in signed accumulation mode.

10: reserved. When set, the device behaves like WATTACC[1:0] = 00.

1:0

WATTACC[1:0]

11: absolute accumulation mode of the total and fundamental active powers. The total and

fundamental energy registers and the CFx pulses are generated in the same way.

00: signed accumulation of the fundamental reactive powers. The fundamental reactive

energy registers and the CFx pulses are generated in the same way.

01: reserved. When set, the device behaves like VARACC[1:0] = 00.

10: the fundamental reactive power is accumulated, depending on the sign of the

fundamental active power: if the active power is positive, the reactive power is accumulated

as is, whereas if the active power is negative, the reactive power is accumulated with reversed

sign. In this mode, although the total and fundamental reactive energy registers are

accumulated in absolute mode, the CFx pulses are generated in signed accumulation mode.

3:2

VARACC[1:0]

11: absolute accumulation mode of the fundamental reactive powers. In this mode,

although the total and fundamental reactive energy registers are accumulated in absolute

mode, the CFx pulses are generated in signed accumulation mode.

These bits select the inputs to the energy accumulation registers. IA’, IB’, and IC’ are IA, IB, and

IC shifted respectively by −90°. See Table 50.

00: 3-phase four wires with three voltage sensors.

01: 3-phase three wires delta connection. In this mode, BVRMS register contains the rms

value of VA-VC.

10: 3-phase four wires with two voltage sensors.

5:4

CONSEL[1:0]

11: 3-phase four wires delta connection.

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