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ADE7880 数据表(PDF) 9 Page - Analog Devices |
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ADE7880 数据表(HTML) 9 Page - Analog Devices |
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9 / 104 page ![]() Data Sheet ADE7880 Rev. A | Page 9 of 104 Table 4. HSDC Interface Timing Parameter Parameter Symbol Min Max Unit HSA to HSCLK Edge tSS 0 ns HSCLK Period 125 ns HSCLK Low Pulse Width tSL 50 ns HSCLK High Pulse Width tSH 50 ns Data Output Valid After HSCLK Edge tDAV 40 ns Data Output Fall Time tDF 20 ns Data Output Rise Time tDR 20 ns HSCLK Rise Time tSR 10 ns HSCLK Fall Time tSF 10 ns HSD Disable After HSA Rising Edge tDIS 5 ns HSA High After HSCLK Edge tSFS 0 ns MSB LSB INTERMEDIATE BITS tSFS tDIS tSS tSL tDF tSH tDAV tSR tSF tDR HSD HSCLK HSA Figure 4. HSDC Interface Timing 2mA IOL 800µA IOH 1.6V TO OUTPUT PIN CL 50pF Figure 5. Load Circuit for Timing Specifications |
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