| 数据搜索系统,热门电子元器件搜索 |
|
ADE7880 数据表(PDF) 67 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADE7880 数据表(HTML) 67 Page - Analog Devices |
|
67 / 104 page ![]() Data Sheet ADE7880 Rev. A | Page 67 of 104 The CFx pulse output is active low and preferably connected to an LED, as shown in Figure 88. VDD CFx PIN Figure 88. CFx Pin Recommended Connection Bits[11:9] (CF3DIS, CF2DIS, and CF1DIS) of the CFMODE register decide if the frequency converter output is generated at the CF3, CF2, or CF1 pin. When Bit CFxDIS is set to 1 (the default value), the CFx pin is disabled and the pin stays high. When Bit CFxDIS is cleared to 0, the corresponding CFx pin output generates an active low signal. Bits[16:14] (CF3, CF2, CF1) in the Interrupt Mask register MASK0 manage the CF3, CF2, and CF1 related interrupts. When the CFx bits are set, whenever a high-to-low transition at the corresponding frequency converter output occurs, an interrupt IRQ0 is triggered and a status bit in the STATUS0 register is set to 1. The interrupt is available even if the CFx output is not enabled by the CFxDIS bits in the CFMODE register. Synchronizing Energy Registers with CFx Outputs The ADE7880 contains a feature that allows synchronizing the content of phase energy accumulation registers with the generation of a CFx pulse. When a high-to-low transition at one frequency converter output occurs, the content of all internal phase energy registers that relate to the power being output at CFx pin is latched into hour registers and then resets to 0. See Table 23 for the list of registers that are latched based on the CFxSEL[2:0] bits in the CFMODE register. All 3-phase registers are latched independent of the TERMSELx bits of the COMPMODE register. The process is shown in Figure 89 for CF1SEL[2:0] = 010 (apparent powers contribute at the CF1 pin) and CFCYC = 2. The CFCYC 8-bit unsigned register contains the number of high to low transitions at the frequency converter output between two consecutive latches. Avoid writing a new value into the CFCYC register during a high-to-low transition at any CFx pin. CFCYC = 2 AVAHR, BVAHR, CVAHR LATCHED ENERGY REGISTERS RESET AVAHR, BVAHR, CVAHR LATCHED ENERGY REGISTERS RESET CF1 PULSE BASED ON PHASE A AND PHASE B APPARENT POWERS Figure 89. Synchronizing AVAHR and BVAHR with CF1 Bits[14:12] (CF3LATCH, CF2LATCH, and CF1LATCH) of the CFMODE register enable this process when set to 1. When cleared to 0, the default state, no latch occurs. The process is available even if the CFx output is not enabled by the CFxDIS bits in the CFMODE register. Energy Registers and CF Outputs for Various Accumulation Modes Bits[1:0] (WATTACC[1:0]) in the ACCMODE register deter- mine the accumulation modes of the total and fundamental active powers when signals proportional to the active powers are chosen at the CFx pins (the CFxSEL[2:0] bits in the CFMODE register equal 000 or 011). They also determine the accumulation modes of the watt-hour energy registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR, BFWATTHR and CFWATTHR). When WATTACC[1:0] = 00 (the default value), the active powers are sign accumulated in the watt-hour registers and before entering the energy-to-frequency converter. Figure 90 shows how signed active power accumulation works. In this mode, the CFx pulses synchronize perfectly with the active energy accumulated in xWATTHR registers because the powers are sign accumulated in both data paths. NEG POS POS APNOLOAD SIGN = POSITIVE NEG NO-LOAD THRESHOLD ACTIVE POWER NO-LOAD THRESHOLD ACTIVE ENERGY REVAPx BIT IN STATUS0 xWSIGN BIT IN PHSIGN Figure 90. Active Power Signed Accumulation Mode When WATTACC[1:0] = 01, the active powers are accumulated in positive only mode. When the powers are negative, the watt- hour energy registers are not accumulated. CFx pulses are generated based on signed accumulation mode. In this mode, the CFx pulses do not synchronize perfectly with the active energy accumulated in xWATTHR registers because the powers are accumulated differently in each data path. Figure 91 shows how positive only active power accumulation works. WATTACC[1:0] = 10 setting is reserved and the ADE7880 behaves identically to the case when WATTACC[1:0] = 00. When WATTACC[1:0] = 11, the active powers are accumulated in absolute mode. When the powers are negative, they change sign and accumulate together with the positive power in the watt-hour registers and before entering the energy-to-frequency |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |