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ADE7880 数据表(PDF) 81 Page - Analog Devices |
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ADE7880 数据表(HTML) 81 Page - Analog Devices |
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81 / 104 page  Data Sheet ADE7880 Rev. A | Page 81 of 104 SILICON ANOMALY This anomaly list describes the known issues with the ADE7880 silicon identified by the Version register (Address 0xE707) being equal to 1. Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended workarounds outlined here. ADE7880 FUNCTIONALITY ISSUES Silicon Revision Identifier Chip Marking Silicon Status Anomaly Sheet No. of Reported Issues Version = 1 ADE7880ACPZ Preliminary Rev. A 4 (er001, er002, er003, er004) FUNCTIONALITY ISSUES Table 26. LAST_ADD Register Shows Wrong Value for Harmonic Calculations Registers in SPI Mode [er001, Version = 1 Silicon] Background When any ADE7880 register is read using SPI or I2C communication, the address is stored in the LAST_ADD register Issue When the harmonic calculation registers located between Address 0xE880 and Address 0xE89F are read using SPI communication, the LAST_ADD register contains the address of the register incremented by 1. The issue is not present if the I2C communication is used. Workaround If the LAST_ADD register is read after one of the registers located between Address 0xE880 and Address 0xE89F was read using SPI communication, subtract 1 from it to recover the right address. Related Issues None. Table 27. To Obtain Best Accuracy Performance, Internal Setting Must Be Changed [er002, Version = 1 Silicon] Background Internal default settings provide best accuracy performance for ADE7880. Issue It was found that if a different setting is used, the accuracy performance can be improved. Workaround To enable a new setting for this internal register, execute three consecutive write operations: The first write operation is to an 8-bit location: 0xAD is written to Address 0xE7FE. The second write operation is to a 16-bit location: 0x3BD is written to Address 0xE90C. The third write operation is to an 8-bit location: 0x00 is written to Address 0xE7EF. The write operations must be executed consecutively without any other read/write operation in between. As a verification that the value was captured correctly, a simple 16-bit read of Address 0xE90C should show the 0x3BD value. Related Issues None. Table 28. High-Pass Filter Cannot be Disabled in Phase C Voltage Data Path [er003, Version = 1 Silicon] Background When Bit 0 (HPFEN) of the CONFIG3 register is 0, all high-pass filters (HPF) in the phase and neutral currents and phase voltages data paths are disabled (see the ADE7880 data sheet for more information about the current channel HPF and the voltage channel HPF). Issue The HPF in the Phase C voltage data path remains enabled independent of the state of Bit HPFEN. Workaround There is no workaround. Related Issues None. |
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