ADE7880 datasheet(76/104 Pages) AD

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ADE7880

Data Sheet

Rev. A | Page 76 of 104

I2C Read Operation of Harmonic Calculations Registers

The registers containing the harmonic calculation results are

located starting at Address 0xE880 and are all 32-bit width.

They can be read in two ways: one register at a time (see the I2C

Read Operation section for details) or multiple consecutive

registers at a time in a burst mode. This burst mode is

accomplished in two stages. As seen in Figure 102, the first

stage sets the pointer to the address of the register and is

identical to the first stage executed when only one register is

read. The second stage reads the content of the registers. The

second stage begins with the master generating a new start

condition followed by an address byte equal to the address byte

used when one single register is read, 0x71. After this byte is

received, the ADE7880 generates an acknowledge. Then, the

ADE7880 sends the value of the first register located at the

pointer, and after every eight bits are received, the master

generates an acknowledge. All the bytes are sent with the most

significant bit first. After the bytes of the first register are sent, if

the master acknowledges the last byte, the ADE7880 increments

the pointer by one location to position it at the next register and

begins to send it out byte by byte, most significant bit first. If the

master acknowledges the last byte, the ADE7880 increments the

pointer again and begins to send data from the next register.

The process continues until the master ceases to generate an

acknowledge at the last byte of the register and then generates a

stop condition. It is recommended to not allow locations greater

then 0xE89F, the last location of the harmonic calculations

registers.

SPI-Compatible Interface

The SPI of the ADE7880 is always a slave of the communication

and consists of four pins (with dual functions): SCLK/SCL,

MOSI/SDA, MISO/HSD, and SS/HSA. The functions used in

the SPI-compatible interface are SCLK, MOSI, MISO, and SS.

The serial clock for a data transfer is applied at the SCLK logic

input. All data transfer operations synchronize to the serial

clock. Data shifts into the

at the MOSI logic input

on the falling edge of SCLK and the

samples it on

the rising edge of SCLK. Data shifts out of the

the MISO logic output on a falling edge of SCLK and can be

sampled by the master device on the raising edge of SCLK. The

most significant bit of the word is shifted in and out first. The

maximum serial clock frequency supported by this interface

is 2.5 MHz. MISO stays in high impedance when no data is

transmitted from the

. See

for details of the

connection between the

SPI and a master device

containing an SPI interface.

ADE7880

Figure 103

ADE7880

The SS logic input is the chip select input. This input is used

when multiple devices share the serial bus. Drive the SS input

low for the entire data transfer operation. Bringing SS high

during a data transfer operation aborts the transfer and places

the serial bus in a high impedance state. A new transfer can

then be initiated by returning the SS logic input to low.

However, because aborting a data transfer before completion

leaves the accessed register in a state that cannot be guaranteed,

every time a register is written, its value should be verified by

reading it back. The protocol is similar to the protocol used in

I2C interface.

MOSI

MISO

SCLK

ADE7880

MOSI

MISO

SCK

SPI DEVICE

Figure 103. Connecting ADE7880 SPI with an SPI Device

SPI Read Operation

The read operation using the SPI interface of the ADE7880

initiate when the master sets the SS/HSA pin low and begins

sending one byte, representing the address of the

, on

the MOSI line. The master sets data on the MOSI line starting

with the first high-to-low transition of SCLK. The SPI of the

samples data on the low-to-high transitions of SCLK.

The most significant seven bits of the address byte can have any

value, but as a good programming practice, they should be

different from 0111000b, the seven bits used in the I2C protocol.

Bit 0 (read/

ADE7880

write) of the address byte must be 1 for a read

operation. Next, the master sends the 16-bit address of the

receives the last bit of

address of the register on a low-to-high transition of SCLK, it

begins to transmit its contents on the MISO line when the next

SCLK high-to-low transition occurs; thus, the master can

sample the data on a low-to-high SCLK transition. After the

master receives the last bit, it sets the

ADE7880

SS and SCLK lines high

and the communication ends. The data lines, MOSI and MISO,

go into a high impedance state. See

for details of the

SPI read operation.

Figure 104

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