ADE7880 datasheet(71/104 Pages) AD

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Data Sheet

ADE7880

Rev. A | Page 71 of 104

CHECKSUM REGISTER

The ADE7880 has a checksum 32-bit register, CHECKSUM, that

ensures the configuration registers maintain their desired value

during Normal Power Mode PSM0.

The registers covered by this register are MASK0, MASK1,

COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,

CONFIG, MMODE, ACCMODE, LCYCMODE, HSDC_CFG,

all registers located in the DSP data memory RAM between

Address 0x4380 and Address 0x43BE and another eight 8-bit

reserved internal registers that always have default values. The

ADE7880 computes the cyclic redundancy check (CRC) based

on the IEEE802.3 standard. The registers are introduced one-by-

one into a linear feedback shift register (LFSR) based generator

starting with the least significant bit (as shown in Figure 96).

The 32-bit result is written in the CHECKSUM register. After

power-up or a hardware/software reset, the CRC is computed

on the default values of the registers giving a result equal to

0xAFFA63B9.

Figure 97 shows how the LFSR works: the MASK0, MASK1,

COMPMODE, Gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,

CONFIG, MMODE, ACCMODE, LCYCMODE, and HSDC_CFG

registers, the registers located between Address 0x4380, and

Address 0x43BE and the eight 8-bit reserved internal registers

form the bits [a2271, a2270,…, a0] used by LFSR. Bit a0 is the least

significant bit of the first register to enter LFSR; Bit a2271 is the

most significant bit of the last register to enter LFSR. The

formulas that govern LFSR are as follows:

•

bi(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits that

form the CRC. Bit b0 is the least significant bit, and Bit b31

is the most significant.

•

gi, i = 0, 1, 2, …, 31 are the coefficients of the generating

polynomial defined by the IEEE802.3 standard as follows:

G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 +

x5 + x4 + x2 + x + 1

(52)

g0 = g1 = g2 = g4 = g5 = g7 = 1

g8 = g10 = g11 = g12 = g16 = g22 = g26 = 1

(53)

All of the other gi coefficients are equal to 0.

FB(j) = aj – 1 XOR b31(j − 1)

(54)

b0(j) = FB(j) AND g0

(55)

bi(j) = FB(j) AND gi XOR bi – 1(j – 1), i = 1, 2, 3, ..., 31

(56)

Equation 54, Equation 55, and Equation 56 must be repeated for

j = 1, 2, …, 2272. The value written into the CHECKSUM register

contains the Bit bi(2272), i = 0, 1, …, 31.

Every time a configuration register of the ADE7880 is written or

changes value inadvertently, the Bit 25 (CRC) in STATUS1 register

is set to 1 to signal CHECKSUM value has changed. If Bit 25 (CRC)

in MASK1 register is set to 1, then the IRQ1 interrupt pin is driven

low and the status flag CRC in STATUS1 is set to 1. The status bit is

cleared and the IRQ1 pin is set to high by writing to the STATUS1

When Bit CRC in STATUS1 is set to 1 without any register

being written, it can be assumed that one of the registers has

changed value and therefore, the ADE7880 has changed

configuration. The recommended response is to initiate a

hardware/software reset that sets the values of all registers to the

default, including the reserved ones, and then reinitialize the

configuration registers.

2271

LFSR

GENERATOR

ARRAY OF 2272 BITS

Figure 96. CHECKSUM Register Calculation

LFSR

g31

b31

a1767, a1766,....,a2, a1, a0

Figure 97. LFSR Generator Used in CHECKSUM Register Calculation

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