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ADE7880 数据表(PDF) 73 Page - Analog Devices |
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ADE7880 数据表(HTML) 73 Page - Analog Devices |
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73 / 104 page  Data Sheet ADE7880 Rev. A | Page 73 of 104 JUMP TO ISR GLOBAL INTERRUPT MASK CLEAR MCU INTERRUPT FLAG READ STATUSx JUMP TO ISR WRITE BACK STATUSx ISR ACTION (BASED ON STATUSx CONTENTS) ISR RETURN GLOBAL INTERRUPT MASK RESET MCU INTERRUPT FLAG SET PROGRAM SEQUENCE t2 t1 t3 IRQx Figure 98. Interrupt Management PROGRAM SEQUENCE IRQx JUMP TO ISR GLOBAL INTERRUPT MASK CLEAR MCU INTERRUPT FLAG READ STATUSx READ PHx JUMP TO ISR WRITE BACK STATUSx ISR ACTION (BASED ON STATUSx CONTENTS) ISR RETURN GLOBAL INTERRUPT MASK RESET MCU INTERRUPT FLAG SET t2 t1 t3 Figure 99. Interrupt Management when PHSTATUS, IPEAK, VPEAK, or PHSIGN Registers are Involved SERIAL INTERFACES The ADE7880 has three serial port interfaces: one fully licensed I2C interface, one serial peripheral interface (SPI), and one high speed data capture port (HSDC). As the SPI pins are multiplexed with some of the pins of the I2C and HSDC ports, the ADE7880 accepts two configurations: one using the SPI port only and one using the I2C port in conjunction with the HSDC port. Serial Interface Choice After reset, the HSDC port is always disabled. Choose between the I2C and SPI ports by manipulating the SS/has pin after power-up or after a hardware reset. If the SS/HSA pin is kept high, then the uses the I2C port until a new hardware reset is executed. If the ADE7880 SS/HSA pin is toggled high to low three times after power-up or after a hardware reset, the uses the SPI port until a new hardware reset is executed. This manipulation of the ADE7880 SS/HSA pin can be accomplished in two ways. First, use the SS/HSA pin of the master device (that is, the microcontroller) as a regular I/O pin and toggle it three times. Second, execute three SPI write operations to a location in the address space that is not allocated to a specific register (for example 0xEBFF, where eight bit writes can be executed). These writes allow the ADE7880 SS/HSA pin to toggle three times. See the section for details on the write protocol involved. SPI Write Operation After the serial port choice is completed, it needs to be locked. Consequently, the active port remains in use until a hardware reset is executed in PSM0 normal mode or until a power-down. If I2C is the active serial port, Bit 1 (I2C_LOCK) of the CONFIG2 register must be set to 1 to lock it in. From this moment, the ADE7880 ignores spurious toggling of the SS pin and an eventual switch into using the SPI port is no longer possible. If the SPI is the active serial port, any write to the CONFIG2 register locks the port. From this moment, a switch into using the I2C port is no longer possible. Once locked, the serial port choice is maintained when the changes PSMx power modes. ADE7880 The functionality of the ADE7880 is accessible via several on- chip registers. The contents of these registers can be updated or read using either the I2C or SPI interfaces. The HSDC port provides the state of up to 16 registers representing instantaneous values of phase voltages and neutral currents, and active, reactive, and apparent powers. Communication Verification The ADE7880 includes a set of three registers that allow any communication via I2C or SPI to be verified. The LAST_OP (Address 0xEA01), LAST_ADD (Address 0xE9FE) and LAST_RWDATA registers record the nature, address and data of the last successful communication respectively. The LAST_RWDATA register has three separate addresses depending on the length of the successful communication. Table 24. LAST_RWDATA Register Locations Communication type Address 8-Bit Read/Write 0xE7FD 16-Bit Read/Write 0xE9FF 24-Bit Read/Write 0xE5FF After each successful communication with the ADE7880, the address of the register that was last accessed is stored in the 16-bit LAST_ADD register (Address 0xE9FE). This is a read only register that stores the value until the next successful read or write is complete. The LAST_OP register (Address 0xEA01) stores the nature of the operation. That is, it indicates whether a read or a write was performed. If the last operation is a write, the LAST_OP register stores the value 0xCA. If the last operation is a read, the LAST_OP register stores the value 0x35. The LAST_RWDATA register stores the data that was written or read from the register. Any unsuccessful read or write operation is not reflected in these registers. When LAST_OP, LAST_ADD and LAST_RWDATA registers are read, their values are not stored into themselves. |
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