ADE7880 datasheet(20/104 Pages) AD

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ADE7880

Data Sheet

Rev. A | Page 20 of 104

POWER MANAGEMENT

The ADE7880 has four modes of operation, determined by the

state of the PM0 and PM1 pins (see Table 8). These pins provide

complete control of the ADE7880 operation and can easily be

connected to an external microprocessor I/O. The PM0 and

PM1 pins have internal pull-up resistors. See Table 10 and Table 11

for a list of actions that are recommended before and after setting

a new power mode.

Table 8. Power Supply Modes

Power Supply Modes

PM1

PM0

PSM0, Normal Power Mode

PSM1, Reduced Power Mode

PSM2, Low Power Mode

PSM3, Sleep Mode

PSM0—NORMAL POWER MODE (ALL PARTS)

In PSM0 mode, the ADE7880 is fully functional. The PM0 pin

is set to high, and the PM1 pin is set to low for the ADE7880 to

enter this mode. If the ADE7880 is in PSM1, PSM2, or PSM3

mode and is switched into PSM0 mode, then all control registers

take the default values with the exception of the threshold register,

LPOILVL, which is used in PSM2 mode, and the CONFIG2

The ADE7880 signals the end of the transition period by triggering

the IRQ1 interrupt pin low and setting Bit 15 (RSTDONE) in the

STATUS1 register to 1. This bit is 0 during the transition period

and becomes 1 when the transition is finished. The status bit is

cleared and the IRQ1 pin is set back to high by writing to the

STATUS1 register with the corresponding bit set to 1. Bit 15

(RSTDONE) in the interrupt mask register does not have any

functionality attached even if the IRQ1 pin goes low when Bit 15

(RSTDONE) in the STATUS1 register is set to 1. This makes the

RSTDONE interrupt unmaskable.

PSM1—REDUCED POWER MODE

In the reduced power mode, PSM1, the ADE7880 measures the

mean absolute values (mav) of the 3-phase currents and stores

the results in the AIMAV, BIMAV, and CIMAV 20-bit registers.

This mode is useful in missing neutral cases in which the voltage

supply of the ADE7880 is provided by an external battery. The

serial ports, I2C or SPI, are enabled in this mode; the active port

can be used to read the AIMAV, BIMAV, and CIMAV registers. It

is not recommended to read any of the other registers because their

values are not guaranteed in this mode. Similarly, a write operation

is not taken into account by the ADE7880 in this mode.

In summary, in this mode, it is not recommended to access any

that computes the rms estimates is also active during PSM0;

therefore, its calibration can be completed in either PSM0 mode

or in PSM1 mode. Note that the ADE7880 does not provide any

calibration process. The external microprocessor stores the gain

values in connection with these measurements and uses them

during PSM1 (see the Current Mean Absolute Value Calculation

section for more details on the xIMAV registers).

The 20-bit mean absolute value measurements done in PSM1,

although available also in PSM0, are different from the rms

measurements of phase currents and voltages executed only in

PSM0 and stored in the HxIRMS and HxVRMS 24-bit registers.

See the Current Mean Absolute Value Calculation section for

details.

If the ADE7880 is set in PSM1 mode after it was in the PSM0

mode, the ADE7880 immediately begins the mean absolute

value calculations without any delay. The xIMAV registers are

accessible at any time; however, if the ADE7880 is set in PSM1

mode after it was in PSM2 or PSM3 modes, the ADE7880

signals the start of the mean absolute value computations by

triggering the IRQ1 pin low. The xIMAV registers can be

accessed only after this moment.

PSM2—LOW POWER MODE

In the low power mode, PSM2, the ADE7880 compares all

phase currents against a threshold for a period of 0.02 ×

(LPLINE[4:0] + 1) seconds, independent of the line frequency.

LPLINE[4:0] are Bits[7:3] of the LPOILVL register (see Table 9).

Table 9. LPOILVL Register

Bit

Mnemonic

Default

Description

[2:0]

LPOIL[2:0]

111

Threshold is put at a value

corresponding to full scale

multiplied by LPOIL/8

[7:3]

LPLINE[4:0]

00000

The measurement period is

(LPLINE[4:0] + 1)/50 sec

The threshold is derived from Bits[2:0] (LPOIL[2:0]) of the

LPOILVL register as LPOIL[2:0]/8 of full scale. Every time

one phase current becomes greater than the threshold, a

counter is incremented. If every phase counter remains below

LPLINE[4:0] + 1 at the end of the measurement period, then

the IRQ0 pin is triggered low. If a single phase counter becomes

greater or equal to LPLINE[4:0] + 1 at the end of the measurement

period, the IRQ1 pin is triggered low.

illustrates how

the

behaves in PSM2 mode when LPLINE[4:0] = 2

and LPOIL[2:0] = 3. The test period is three 50 Hz cycles (60 ms),

and the Phase A current rises above the LPOIL[2:0] threshold three

times. At the end of the test period, the

Figure 33

ADE7880

IRQ1 pin is triggered low.

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