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ADE7880 数据表(PDF) 95 Page - Analog Devices |
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ADE7880 数据表(HTML) 95 Page - Analog Devices |
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95 / 104 page ![]() Data Sheet ADE7880 Rev. A| Page 95 of 104 Bit Mnemonic Default Value Description 4 FNLPHASE[1] 0 0: Phase B is out of no load condition based on fundamental active/reactive powers. 1: Phase B is in no load condition based on fundamental active/reactive powers. This bit is set together with Bit 1 (FNLOAD) in STATUS1. 5 FNLPHASE[2] 0 0: Phase C is out of no load condition based on fundamental active/reactive powers. 1: Phase C is in no load condition based on fundamental active/reactive powers. This bit is set together with Bit 1 (FNLOAD) in STATUS1. 6 VANLPHASE[0] 0 0: Phase A is out of no load condition based on apparent power. 1: Phase A is in no load condition based on apparent power. Bit set together with Bit 2 (VANLOAD) in the STATUS1 register. 7 VANLPHASE[1] 0 0: Phase B is out of no load condition based on apparent power. 1: Phase B is in no load condition based on apparent power. Bit set together with Bit 2 (VANLOAD) in the STATUS1 register. 8 VANLPHASE[2] 0 0: Phase C is out of no load condition based on apparent power. 1: Phase C is in no load condition based on apparent power. Bit set together with Bit 2 (VANLOAD) in the STATUS1 register. 15:9 Reserved 000 0000 Reserved. These bits are always 0. Table 42. COMPMODE Register (Address 0xE60E) Bit Mnemonic Default Value Description 0 TERMSEL1[0] 1 Setting all TERMSEL1[2:0] to 1 signifies the sum of all three phases is included in the CF1 output. Phase A is included in the CF1 outputs calculations. 1 TERMSEL1[1] 1 Phase B is included in the CF1 outputs calculations. 2 TERMSEL1[2] 1 Phase C is included in the CF1 outputs calculations. 3 TERMSEL2[0] 1 Setting all TERMSEL2[2:0] to 1 signifies the sum of all three phases is included in the CF2 output. Phase A is included in the CF2 outputs calculations. 4 TERMSEL2[1] 1 Phase B is included in the CF2 outputs calculations. 5 TERMSEL2[2] 1 Phase C is included in the CF2 outputs calculations. 6 TERMSEL3[0] 1 Setting all TERMSEL3[2:0] to 1 signifies the sum of all three phases is included in the CF3 output. Phase A is included in the CF3 outputs calculations. 7 TERMSEL3[1] 1 Phase B is included in the CF3 outputs calculations. 8 TERMSEL3[2] 1 Phase C is included in the CF3 outputs calculations. 10:9 ANGLESEL[1:0] 00 00: the angles between phase voltages and phase currents are measured. 01: the angles between phase voltages are measured. 10: the angles between phase currents are measured. 11: no angles are measured. 11 VNOMAEN 0 When this bit is 0, the apparent power on Phase A is computed regularly. When this bit is 1, the apparent power on Phase A is computed using VNOM register instead of regular measured rms phase voltage. 12 VNOMBEN 0 When this bit is 0, the apparent power on Phase B is computed regularly. When this bit is 1, the apparent power on Phase B is computed using VNOM register instead of regular measured rms phase voltage. 13 VNOMCEN 0 When this bit is 0, the apparent power on Phase C is computed regularly. When this bit is 1, the apparent power on Phase C is computed using VNOM register instead of regular measured rms phase voltage. 14 SELFREQ 0 When the ADE7880 is connected to 50 Hz networks, this bit should be cleared to 0 (default value). When the ADE7880 is connected to 60 Hz networks, this bit should be set to 1. 15 Reserved 0 This bit is 0 by default and it does not manage any functionality. |
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