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ADE7880 数据表(PDF) 101 Page - Analog Devices |
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ADE7880 数据表(HTML) 101 Page - Analog Devices |
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101 / 104 page  Data Sheet ADE7880 Rev. A| Page 101 of 104 Bit Mnemonic Default Value Description 7 PFMODE 0 0: power factor calculation uses instantaneous values of various phase powers used in its expression. 1: power factor calculation uses phase energies values calculated using line cycle accumulation mode. Bits LWATT and LVA in LCYCMODE register must be enabled for the power factors to be computed correctly. The update rate of the power factor measurement in this case is the integral number of half line cycles that are programmed into the LINECYC register. Table 52. HSDC_CFG Register (Address 0xE706) Bit Mnemonic Default Value Description 0 HCLK 0 0: HSCLK is 8 MHz. 1: HSCLK is 4 MHz. 1 HSIZE 0 0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first. 1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first. 2 HGAP 0 0: no gap is introduced between packages. 1: a gap of seven HCLK cycles is introduced between packages. 4:3 HXFER[1:0] 00 00 = HSDC transmits sixteen 32-bit words in the following order: IAWV, VAWV, IBWV, VBWV, ICWV, VCWV, INWV, AVA, BVA, CVA, AWATT, BWATT, CWATT, AFVAR, BFVAR, and CFVAR. 01 = HSDC transmits seven instantaneous values of currents and voltages: IAWV, VAWV, IBWV, VBWV, ICWV, VCWV, and INWV. 10 = HSDC transmits nine instantaneous values of phase powers: AVA, BVA, CVA, AWATT, BWATT, CWATT, AFVAR, BFVAR, and CFVAR. 11 = reserved. If set, the ADE7880 behaves as if HXFER[1:0] = 00. 5 HSAPOL 0 0: SS/has output pin is active low. 1: SS/HSA output pin is active high. 7:6 Reserved 00 Reserved. These bits do not manage any functionality. Table 53. CONFIG3 Register (Address 0xEA00) Bit Mnemonic Default Value Description 0 HPFEN 1 When HPFEN = 1, then all high-pass filters in voltage and current channels are enabled. When HPFEN = 0, then all high-pass filters are disabled. 1 LPFSEL 0 When LPFSEL = 0, the LPF in the total active power data path introduces a settling time of 650 ms. When LPFSEL = 1, the LPF in the total active power data path introduces a settling time of 1300 ms. 2 INSEL 0 When INSEL = 0, the register NIRMS contains the rms value of the neutral current. When INSEL = 1, the register NIRMS contains the rms value of ISUM, the instantaneous value of the sum of all 3 phase currents, IA, IB, and IC. 3 ININTEN 0 This bit manages the integrator in the neutral current channel. If ININTEN = 0, then the integrator in the neutral current channel is disabled. If ININTDIS = 1, then the integrator in the neutral channel is enabled. The integrators in the phase currents channels are managed by Bit 0 (INTEN) of CONFIG register. 4 Reserved 0 Reserved. This bit should be maintained at 0 for proper operation. 7:5 Reserved 000 Reserved. These bits do not manage any functionality. |
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