ADE7932 datasheet(40/120 Pages) AD

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ADE7978/ADE7933/ADE7932

Data Sheet

Rev. 0 | Page 40 of 120

PHASE COMPENSATION

Typically, phase compensation is not needed in the

ADE7978/ADE7933/ADE7932 chipset. As described in the

Current Channel ADC and Voltage Channel ADC sections, the

same datapath is used for the phase current and phase voltages;

therefore, no phase error exists between the phase current and

voltage signals introduced by the ADE7978. In addition, shunts

are used with the ADE7933/ADE7932 devices to sense the phase

currents, eliminating the need for phase compensation.

The ADE7978 provides a means of digitally calibrating eventual

phase mismatch errors. The ADE7978 allows a small time delay

or time advance to be introduced into the signal processing chain

to compensate for the small phase errors.

The 10-bit phase calibration registers (APHCAL, BPHCAL, and

CPHCAL) can vary the time advance in the voltage channel signal

path from −374.0 µs to +374.0 μs. Negative values written to the

xPHCAL registers represent a time advance, whereas positive

values represent a time delay. One LSB is equivalent to 0.976 µs of

time delay or time advance (assuming a clock rate of 1.024 MHz).

With a line frequency of 60 Hz, this calibration gives a phase reso-

lution of 0.0211° (360° × 60 Hz/1.024 MHz) at the fundamental

and corresponds to a total correction range of −8.079° to +8.079°

at 60 Hz. With a line frequency of 50 Hz, the correction range

is −6.732° to +6.732°, and the resolution is 0.0176° (360° ×

50 Hz/1.024 MHz).

Given a phase error of x degrees, measured using the phase

voltage as the reference, the corresponding LSBs are computed

by dividing x by the phase resolution (0.0211°/LSB for 60 Hz

and 0.0176°/LSB for 50 Hz). Only results from −383 to +383 are

allowed; values outside this range are not allowed.

If the current leads the voltage, the result is negative, and the

absolute value is written to the xPHCAL registers. If the current

lags the voltage, the result is positive and 512 is added to the

result before it is written to the xPHCAL registers.

APHCAL, BPHCAL, or CHPCAL =

(13)





















≤

512

resolution

phase

resolution

phase

Figure 52 illustrates the use of phase compensation to remove an

x = −1° phase lead in IA of the current channel from the external

current transducer (equivalent of 55.5 µs for 50 Hz systems). To

cancel the lead (1°) in the current channel of Phase A, a phase

lead must be introduced into the corresponding voltage channel.

Using Equation 13, APHCAL is 57 LSBs, rounded up from 56.8.

The phase lead is achieved by introducing a time delay of 55.73 µs

into the Phase A current.

The serial ports of the ADE7978 work with 32-, 16-, or 8-bit

words, whereas the DSP works with 28-bit words. As shown

in Figure 51, the 10-bit APHCAL, BPHCAL, and CPHCAL

registers are accessed as 16-bit registers with the six MSBs

padded with 0s.

0000 00

10 9

xPHCAL

Figure 51. 10-Bit xPHCAL Register Transmitted as a 16-Bit Word

PHASE COMPENSATION

ACHIEVED DELAYING

IA BY 56µs

50Hz

1°

Σ-Δ

MODULATOR

Σ-Δ

MODULATOR

V1P

PHASE A

ADE7933

ADE7978

PHASE

CALIBRATION

APHCAL = 57

Figure 52. Phase Calibration Process

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