ADE7932 datasheet(46/120 Pages) AD

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ADE7978/ADE7933/ADE7932

Data Sheet

Rev. 0 | Page 46 of 120

If Bit 16 (sag) in the MASK1 register is set and a sag event

occurs, the IRQ1 interrupt pin is driven low at the same time

that Bit 16 (sag) in the STATUS1 register is set to 1. The sag bit

in the STATUS1 register and the IRQ1 pin are returned high by

writing a 1 to Bit 16 in the STATUS1 register.

Note that the internal zero-crossing counter is always active. When

the SAGLVL register is set, the first sag detection result is, therefore,

not executed across a full SAGCYC period. Writing to the SAGCYC

zero-crossing counter, thus ensuring that the first sag detection

result is obtained across a full SAGCYC period.

The recommended procedure to manage sag events is as follows:

1. Configure Bit 6 (SAGCFG) in the ACCMODE register to

select the desired behavior of the sag status bit (Bit 16) in

the STATUS1 register.

2. Enable sag interrupts in the MASK1 register by setting Bit 16

(sag) to 1. When a sag event occurs, the IRQ1 interrupt pin

goes low, and Bit 16 (sag) in the STATUS1 register is set to 1.

3. Read the STATUS1 register to verify that Bit 16 is set to 1.

4. Read the PHSTATUS register (Bits[14:12]) to identify the

phase or phases on which the sag event occurred.

5. Write to the STATUS1 register with Bit 16 (sag) set to 1.

The sag bit is erased immediately.

Sag Detection Level Setting

The contents of the sag level register (SAGLVL[23:0]) are

compared to the absolute value of the output from the HPF.

Writing 5,320,000 to the SAGLVL register sets the sag detection

level to full scale (see the Voltage Channel ADC section); there-

fore, the sag event is triggered continuously. Writing 0x00 or

0x01 to the SAGLVL register sets the sag detection level to 0;

therefore, the sag event is never triggered.

0000 0000

24-BIT NUMBER

24 23

Figure 61. 24-Bit SAGLVL Register Transmitted as a 32-Bit Word

The serial ports of the ADE7978 work with 32-, 16-, or 8-bit

words. The SAGLVL register is transmitted as a 32-bit register

with the eight MSBs padded with 0s (see Figure 61).

PEAK DETECTION

The ADE7978 records the maximum absolute values reached by

the phase current and voltage channels over a specified number

of half line cycles and stores them in the least significant 24 bits

of the 32-bit IPEAK and VPEAK registers (Address 0xE500 and

Address 0xE501).

The PEAKCYC register (Address 0xE703) contains the number

of half line cycles used as a time base for the measurement. The

circuit uses the zero-crossing points identified by the zero-crossing

detection circuit. Bits[4:2] (PEAKSEL[2:0]) in the MMODE

measurement is performed. Bit 2 selects Phase A, Bit 3 selects

Phase B, and Bit 4 selects Phase C.

Selecting more than one phase to monitor the peak values

decreases proportionally the measurement period specified in

the PEAKCYC register because zero crossings from more than

one phase are involved in the process. When a new peak value is

determined, Bits[26:24] (IPPHASE[2:0]) in the IPEAK register

or Bits[26:24] (VPPHASE[2:0]) in the VPEAK register identify

the phase that triggered the peak detection event.

For example, if a peak value is identified on the Phase A current,

Bit 24 (IPPHASE[0]) in the IPEAK register is set to 1. If a new

peak value is then measured on Phase B, Bit 24 (IPPHASE[0])

of the IPEAK register is cleared to 0, and Bit 25 (IPPHASE[1])

is set to 1. Figure 62 shows the composition of the IPEAK and

VPEAK registers.

PEAK DETECTED

ON PHASE C

00000

27 26 25 24 23

24-BIT UNSIGNED NUMBER

PEAK DETECTED

ON PHASE A

IPPHASE/VPPHASE BITS

PEAK DETECTED

ON PHASE B

Figure 62. Composition of IPEAK[31:0] and VPEAK[31:0] Registers

Figure 63 shows how the ADE7978 records the peak value on

the current channel when measurements on Phase A and Phase B

are enabled (PEAKSEL[2:0] bits in the MMODE register are set

to 011).

PHASE A

CURRENT

PHASE B

CURRENT

BIT 24

OF IPEAK

BIT 25

OF IPEAK

PEAK VALUE WRITTEN INTO

IPEAK AT THE END OF FIRST

PEAKCYC PERIOD

END OF FIRST

PEAKCYC = 16 PERIOD

BIT 24 OF IPEAK

CLEARED TO 0 AT

THE END OF SECOND

PEAKCYC PERIOD

BIT 25 OF IPEAK

SET TO 1 AT THE

END OF SECOND

PEAKCYC PERIOD

END OF SECOND

PEAKCYC = 16 PERIOD

PEAK VALUE WRITTEN INTO

IPEAK AT THE END OF

SECOND PEAKCYC PERIOD

Figure 63. Peak Level Detection

In this example, PEAKCYC is set to 16, meaning that the peak

measurement cycle is four line periods. The maximum absolute

value of Phase A is greatest during the first four line periods

(PEAKCYC = 16); therefore, the maximum absolute value is

written to the least significant 24 bits of the IPEAK register, and

Bit 24 (IPPHASE[0]) of the IPEAK register is set to 1 at the end

of the period. This bit remains set to 1 for the duration of the

second PEAKCYC period of four line cycles.

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