ADE7932 datasheet(68/120 Pages) AD

68 / 120 page

ADE7978/ADE7933/ADE7932

Data Sheet

Rev. 0 | Page 68 of 120

ENERGY-TO-FREQUENCY CONVERSION

The ADE7978 provides three frequency output pins: CF1, CF2,

and CF3. The CF3 pin is multiplexed with the HSCLK pin of the

HSDC interface. When HSDC is enabled, the CF3 functionality

is disabled at the pin. The CF1 and CF2 pins are always available.

After initial calibration at manufacturing, the manufacturer or

end customer verifies the energy meter calibration. One conve-

nient way to verify the meter calibration is to provide an output

frequency proportional to the active, reactive, or apparent power

under steady load conditions. This output frequency can provide

a simple, single-wire, optically isolated interface to external cali-

bration equipment. Figure 84 illustrates the energy-to-frequency

conversion in the ADE7978.

The DSP computes the instantaneous values of all phase

powers: total active, fundamental active, total reactive, funda-

mental reactive, and apparent. For information about how the

energy is sign accumulated in the xWATTHR, xFWATTHR,

xVARHR, xFVARHR, and xVAHR registers, see the Active

Energy Calculation, Reactive Energy Calculation, and Apparent

Energy Calculation sections.

In the energy-to-frequency conversion process, the instanta-

neous powers generate signals at the frequency output pins

(CF1, CF2, and CF3). One energy-to-frequency converter is

used for every CFx pin. Each converter sums certain phase

powers and generates a signal proportional to the sum.

Two sets of bits specify the powers that are converted on the

CFx pins: the TERMSELx[2:0] bits and the CFxSEL[2:0] bits.

TERMSELx[2:0] BITS

Bits[2:0] (TERMSEL1[2:0]), Bits[5:3] (TERMSEL2[2:0]),

and Bits[8:6] (TERMSEL3[2:0]) of the COMPMODE register

(Address 0xE60E) specify which phases are summed in the

energy-to-frequency conversion.

•

The TERMSEL1[2:0] bits configure the CF1 pin.

•

The TERMSEL2[2:0] bits configure the CF2 pin.

•

The TERMSEL3[2:0] bits configure the CF3 pin.

The TERMSELx[0] bits manage Phase A. When these bits are

set to 1, Phase A power is included in the sum of powers at the

CFx converter; when these bits are cleared to 0, Phase A power

is not included in the sum of powers. The TERMSELx[1] bits

manage Phase B, and the TERMSELx[2] bits manage Phase C.

Setting all TERMSELx[2:0] bits to 1 means that the powers

from all three phases are added at the CFx converter. Clearing

all TERMSELx[2:0] bits to 0 means that no phase power is

added at the CFx converter and no CF pulse is generated.

CFxSEL[2:0] BITS

Bits[2:0] (CF1SEL[2:0]), Bits[5:3] (CF2SEL[2:0]), and Bits[8:6]

(CF3SEL[2:0]) in the CFMODE register (Address 0xE610)

specify what type of power is used at the inputs of the CF1, CF2,

and CF3 converters, respectively (see Table 28).

WATT

VAR

FVAR

FWATT

CFxSEL BITS IN

CFMODE

INSTANTANEOUS

PHASE A

ACTIVE POWER

DIGITAL SIGNAL

PROCESSOR

INSTANTANEOUS

PHASE B

ACTIVE POWER

INSTANTANEOUS

PHASE C

ACTIVE POWER

TERMSELx BITS IN

COMPMODE

INTERNAL

ACCUMULATOR

THRESHOLD

FREQUENCY

DIVIDER

CFx PULSE

OUTPUT

CFxDEN

WTHR

27 26

REVPSUMx BIT OF

STATUS0[31:0]

Figure 84. Energy-to-Frequency Conversion

Table 28. Description of the CFxSEL[2:0] Bits in the CFMODE Register

CFxSEL[2:0]

CFx Signal Proportional to the Sum of

Registers Latched When CFxLATCH = 1

000

Total phase active powers

AWATTHR, BWATTHR, CWATTHR

001

Total phase reactive powers

AVARHR, BVARHR, CVARHR

010

Phase apparent powers

AVAHR, BVAHR, CVAHR

011

Fundamental phase active powers

AFWATTHR, BFWATTHR, CFWATTHR

100

Fundamental phase reactive powers

AFVARHR, BFVARHR, CFVARHR

101 to 111

Reserved

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