ADE7932 datasheet(98/120 Pages) AD

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ADE7978/ADE7933/ADE7932

Data Sheet

Rev. 0 | Page 98 of 120

CHECKSUM REGISTER

The ADE7978 has a 32-bit checksum register (Address 0xE532)

to ensure that the configuration registers maintain their desired

values. The checksum register verifies all configuration registers

of the ADE7978, as well as the reserved internal registers, which

always maintain their default values.

The ADE7978 computes the cyclic redundancy check (CRC)

based on the IEEE 802.3 standard. The registers are introduced

one by one into a linear feedback shift register (LFSR) generator

starting with the least significant bit (see Figure 127). The 32-bit

result is written to the checksum register. After power-up or after

a hardware or software reset, the CRC is computed on the default

values of the registers, giving a result equal to 0x6BF87803.

2399

LFSR

GENERATOR

ARRAY OF 2400 BITS

Figure 127. Checksum Register Calculation

Figure 128 shows how the LFSR generator is used in the CRC

calculation. The configuration registers and the reserved

internal registers form the bits (a2399, a2398,…, a0) used by the

LFSR generator. Bit a0 is the least significant bit of the first

significant bit of the last register to enter the LFSR generator.

The formulas that govern the LFSR generator are as follows:



bi(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits that

form the CRC. Bit b0 is the least significant bit, and Bit b31

is the most significant bit.



gi, i = 0, 1, 2, …, 31 are the coefficients of the generating

polynomial defined by the IEEE 802.3 standard as follows:

G(x)

(56)

x32

+ x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 +

+ x2 + x + 1

= g1 = g2 = g4 = g5 = g7 = 1

(57)

= g10 = g11 = g12 = g16 = g22 = g23 = g26 = 1

All other gi coefficients are equal to 0.

(j) = aj − 1 XOR b31(j − 1)

(58)

(j) = FB(j) AND g0

(59)

bi(j)

= FB(j) AND gi XOR bi − 1(j − 1), i = 1, 2, 3, ..., 31

(60)

Equation 58, Equation 59, and Equation 60 must be repeated

for j = 1, 2, …, 2400. The value written to the checksum register

contains the Bits bi(2400), i = 0, 1, …, 31.

Every time a configuration register of the ADE7978 is written

to or changes value inadvertently, Bit 25 (CRC) in the STATUS1

value has changed. If Bit 25 (CRC) in the MASK1 register is set

to 1, the IRQ1 interrupt pin is driven low, and the status flag

CRC in the STATUS1 register is set to 1. The status bit is cleared

and the IRQ1 pin returns high after a 1 is written to the CRC

status bit in the STATUS1 register.

If the CRC bit in the STATUS1 register is set to 1 when no register

was written to, it can be assumed that one of the registers has

changed value and, therefore, the configuration of the ADE7978

has changed. The recommended response is to initiate a hard-

ware or software reset to reset all registers, including reserved

registers, to their default values, and then to reinitialize the

configuration registers.

For more information, see the Hardware Reset and

ADE7978/ADE7933/ADE7932 Chipset Software Reset sections.

LFSR

g31

b31

a2399, a2398, ..., a2, a1, a0

Figure 128. LFSR Generator Used in Checksum Register Calculation

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