ADE7932 datasheet(77/120 Pages) AD

77 / 120 page

Data Sheet

ADE7978/ADE7933/ADE7932

Rev. 0 | Page 77 of 120

POWER MANAGEMENT

DC-TO-DC CONVERTER

The dc-to-dc converter section of the ADE7933/ADE7932 works

on principles that are common to most modern power supply

designs. VDD power is supplied to an oscillating circuit that

switches current into a chip scale air core transformer. Power is

transferred to the secondary side, where it is rectified to a 3.3 V

dc voltage. This voltage is then supplied to the ADC section of

the ADE7933/ADE7932 through a 2.5 V LDO regulator.

The state of the internal dc-to-dc converter in the ADE7933/

ADE7932 is controlled by the VDD input. In normal opera-

tional mode, maintain VDD at a voltage from 2.97 V to 3.63 V.

Figure 95 is a block diagram of the ADE7933/ADE7932 isolated

dc-to-dc converter. The primary supply voltage input (VDD)

supplies an ac source. The ac signal passes through a chip scale

air core transformer and is transferred to the secondary side. A

rectifier then produces the isolated power supply, VDDISO. Using

another chip scale air core transformer, a feedback circuit measures

VDDISO and passes the information back to the VDD domain,

where a PWM control block controls the ac source to maintain

VDDISO at 3.3 V.

AC SOURCE

ISOLATION

BARRIER

RECTIFIER

VDDISO

FEEDBACK

CIRCUIT

PWM

CONTROL

TO ADC

BLOCK

VDD = 3.3V

Figure 95. Isolated DC-to-DC Converter Block Diagram

The PWM control block operates at a frequency of 1.024 MHz

(CLKIN/4). Every other half period, the control block generates a

PWM pulse to the ac source based on the state of the EMI_CTRL

pin (see Figure 96).

PWM CONTROL PULSE

WHEN EMI_CTRL = GND

PWM CONTROL PULSE

WHEN EMI_CTRL = VDD

1.024MHz CLOCK

Figure 96. PWM Control Block Generates Pulses Based on 1.024 MHz Clock

Each time a PWM pulse is generated, the ac source transmits

very high frequency signals across the isolation barrier to allow

efficient power transfer through the small chip scale transformers.

This transfer creates high frequency currents that can propagate

in circuit board ground and power planes, causing edge and

dipole radiation.

To manage electromagnetic interference (EMI) issues, attention

must be paid to proper PCB layout. The Layout Guidelines

section describes the best approach to PCB layout. In addition

to creating a well-designed PCB layout, the designer can use the

EMI_CTRL pin to help reduce the emissions generated by the

dc-to-dc converter of the ADE7933/ADE7932.

Every four periods of the clock that manages the PWM control

block are divided into eight slots, Slot 0 to Slot 7 (see Figure 96).

When the EMI_CTRL pin is connected to GND, the PWM

control block generates pulses during Slot 0, Slot 2, Slot 4, and

Slot 6. When the EMI_CTRL pin is connected to VDD, the PWM

control block generates pulses during Slot 1, Slot 3, Slot 5, and

Slot 7. Table 34 describes the recommended connections for the

EMI_CTRL pin in all configurations of a 3-phase energy meter.

Table 34. Connection of EMI_CTRL Pins

No. of ADE7933/

ADE7932 Devices

EMI_CTRL Pin Connections

Connect the pin to GND

Connect the pin to GND on one device;

connect the pin to VDD on the other device

Connect the pin to GND on two devices;

connect the pin to VDD on the third device

Connect the pin to GND on two devices;

connect the pin to VDD on the other devices

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