ADE7932 datasheet(41/120 Pages) AD

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Data Sheet

ADE7978/ADE7933/ADE7932

Rev. 0 | Page 41 of 120

DIGITAL SIGNAL PROCESSOR

The ADE7978 contains a fixed function digital signal processor

(DSP) that computes all powers and rms values. The DSP con-

tains program memory ROM and data memory RAM.

Program memory ROM stores the program used for the power

and rms computations; the processor executes the program every

8 kHz. The end of the computations is signaled by setting Bit 17

(DREADY) to 1 in the STATUS0 register (Address 0xE502). An

interrupt attached to this flag can be enabled by setting Bit 17

(DREADY) in the MASK0 register (Address 0xE50A).

When the interrupt is enabled, the IRQ0 pin is set low and the

DREADY status bit is set to 1 at the end of the computations.

The status bit is cleared and the IRQ0 pin returns high when

a 1 is written to Bit 17 (DREADY) in the STATUS0 register.

In addition, when Bits[1:0] (ZX_DREADY) in the CONFIG

is selected at the ZX/DREADY pin. In this case, the ZX/DREADY

pin goes low approximately 70 ns after the DREADY bit is set to

1 in the STATUS0 register. The ZX/DREADY pin stays low for

10 µs and then returns high.

The low to high transition of the ZX/DREADY pin can be used

to initiate a burst read of the waveform sample registers. For more

information, see the I2C Burst Read Operation and the SPI Burst

Read Operation sections. For information about using the ZX

functionality at the ZX/DREADY pin (ZX_DREADY bits in the

CONFIG register are set to 01, 10, or 11), see the Zero-Crossing

Detection section.

The registers used as inputs by the DSP are located in the data

memory RAM at addresses from 0x4380 to 0x43BF. The width

of this memory is 28 bits. Within the DSP core, the DSP contains

a two-stage pipeline. This means that when a single register must

be initialized, two more writes are required to ensure that the

value is written into RAM, and if two or more registers must be

initialized, the last register must be written two more times to

ensure that the values are written into RAM.

At power-up or after a hardware or software reset, the DSP is in

idle mode. No instruction is executed. All registers located in

the data memory RAM are initialized to 0, their default values,

and they can be read or written without any restriction. The run

DSP, is cleared to 0x0000.

The run register must be written with 0x0001 for the DSP to start

code execution. Before writing 0x0001 to the run register, it is

recommended that all ADE7978 registers located in the data

memory RAM be initialized to their desired values. Next, write

the last register in the queue two additional times to flush the

pipeline, and then write 0x0001 to the run register. In this way,

the DSP starts the computations from a desired configuration.

To protect the integrity of the data stored in the data memory RAM

of the DSP (addresses from 0x4380 to 0x43BF), a write protection

mechanism is available. By default, the protection is disabled and

registers located from Address 0x4380 to Address 0x43BF can be

written without restriction. When the protection is enabled, no

writes to these registers are allowed. Registers can always be read

without restriction, independent of the write protection state.

To enable the protection, write 0xAD to the internal 8-bit register

located at Address 0xE7FE, followed by a write of 0x80 to the

internal 8-bit register located at Address 0xE7E3.

It is recommended that the write protection be enabled after the

registers are initialized. If any data memory RAM-based register

must be changed, disable the protection, change the value, and

then reenable the protection. There is no need to stop the DSP

to change these registers.

To disable the protection, write 0xAD to the internal 8-bit

to the internal 8-bit register located at Address 0xE7E3.

The recommended procedure for initializing the registers

located in the data memory RAM at power-up is described in

the Initializing the Chipset section.

In the unlikely event that one or more registers are not initialized

correctly, disable the protection by writing 0xAD to the internal

8-bit register located at Address 0xE7FE, followed by a write of

0x00 to the internal 8-bit register located at Address 0xE7E3.

Reinitialize the registers, writing the last register in the queue three

times. Enable the write protection by writing 0xAD to the internal

8-bit register located at Address 0xE7FE, followed by a write of

0x80 to the internal 8-bit register located at Address 0xE7E3.

There is no obvious reason to stop the DSP. All ADE7978

registers, including the registers located in the data memory RAM,

can be modified without stopping the DSP. However, to stop the

DSP, 0x0000 must be written to the run register. To restart the DSP,

one of the following procedures must be followed:

•

If the ADE7978 registers located in the data memory RAM

have not been modified, write 0x0001 to the run register to

start the DSP.

•

If the ADE7978 registers located in the data memory RAM

must be modified, execute a software or a hardware reset,

initialize all ADE7978 registers at the desired values, enable

the write protection, and then write 0x0001 into the run

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