ADE7932 datasheet(96/120 Pages) AD

96 / 120 page

ADE7978/ADE7933/ADE7932

Data Sheet

Rev. 0 | Page 96 of 120

HSDC INTERFACE

The high speed data capture (HSDC) interface is disabled by

default. It can be used only when the ADE7978 is configured for

the I2C interface. The SPI interface of the ADE7978 cannot be

used at the same time as the HSDC interface.

When Bit 6 (HSDCEN) is set to 1 in the CONFIG register, the

HSDC interface is enabled. If the HSDCEN bit is cleared to 0

(the default value), the HSDC interface is disabled. Setting this

bit to 1 when the SPI interface is in use has no effect on the part.

The HSDC interface is used to send data to an external device

(usually a microprocessor or a DSP); this data can consist of up

to sixteen 32-bit words. The words represent the instantaneous

values of the phase currents and voltages, neutral current, and

active, reactive, and apparent powers. The registers transmitted

are IAWV, VAWV, IBWV, VBWV, ICWV, VCWV, INWV, AVA,

BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR, and

CVAR. These 24-bit registers are sign extended to 32 bits

(see Figure 45).

HSDC can interface with SPI or similar interfaces; HSDC is

always the master of the communication. The HSDC interface

consists of three pins: HSA, HSD, and HSCLK. HSA represents

the select signal. It stays active low or high when a word is trans-

mitted and is usually connected to the select pin of the slave. HSD

sends data to the slave and is usually connected to the data input

pin of the slave. HSCLK is the serial clock line that is generated

by the ADE7978; HSCLK is usually connected to the serial clock

input of the slave. Figure 123 shows the connections between

the ADE7978 HSDC interface and a slave device containing an

SPI interface.

ADE7978

HSD

MOSI

HSCLK

SCK

HSA

SPI DEVICE

Figure 123. Connecting the ADE7978 HSDC Interface to an SPI Slave

HSDC communication is managed by the HSDC_CFG register

(see Table 58). It is recommended that the HSDC_CFG register

be set to the desired value before the HSDC port is enabled using

Bit 6 (HSDCEN) in the CONFIG register. In this way, the state

of various pins belonging to the HSDC port do not accept levels

inconsistent with the desired HSDC behavior. After a hardware

reset or after power-up, the HSD and HSA pins are set high.

Bit 0 (HCLK) in the HSDC_CFG register determines the serial

clock frequency of the HSDC communication. When the HCLK

bit is set to 0 (the default value), the clock frequency is 8 MHz.

When the HCLK bit is set to 1, the clock frequency is 4 MHz. A

bit of data is transmitted at every HSCLK high to low transition.

The slave device that receives data from the HSDC interface

samples the HSD line on the low to high transition of HSCLK.

The words can be transmitted as 32-bit packages or as 8-bit

packages. When Bit 1 (HSIZE) in the HSDC_CFG register is

set to 0 (the default value), the words are transmitted as 32-bit

packages. When the HSIZE bit is set to 1, the registers are

transmitted as 8-bit packages. The HSDC interface transmits

the words MSB first.

When set to 1, Bit 2 (HGAP) introduces a gap of seven HSCLK

cycles between packages. When the HGAP bit is cleared to 0 (the

default value), no gap is introduced between packages, yielding

the shortest communication time. When HGAP is set to 0, the

HSIZE bit has no effect on the communication, and a data bit is

placed on the HSD line at every HSCLK high to low transition.

Bits[4:3] (HXFER[1:0]) specify how many words are transmitted.

When HXFER[1:0] is set to 00 (the default value), all 16 words

are transmitted. When HXFER[1:0] is set to 01, only the words

representing the instantaneous values of phase and neutral

currents and phase voltages are transmitted in the following

order: IAWV, VAWV, IBWV, VBWV, ICWV, VCWV, and

INWV. When HXFER[1:0] is set to 10, only the instantaneous

values of phase powers are transmitted in the following order:

AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR, and

CVAR. The value 11 for HXFER[1:0] is reserved, and writing it

is equivalent to writing 00, the default value.

Bit 5 (HSAPOL) specifies the polarity of the HSA function on

the HSA pin during communication. When the HSAPOL bit is

set to 0 (the default value), the HSA pin is active low during the

communication; that is, HSA stays high when no communication

is in progress. When a communication is executed, HSA is low

when the 32-bit or 8-bit packages are transferred and high during

the gaps. When the HSAPOL bit is set to 1, the HSA pin is active

high during the communication; that is, HSA stays low when no

communication is in progress. When a communication is executed,

HSA is high when the 32-bit or 8-bit packages are transferred and

is low during the gaps.

Bits[7:6] of the HSDC_CFG register are reserved. Any value

written into these bits has no effect on HSDC behavior.

Figure 124 shows the HSDC transfer protocol for HGAP = 0,

HXFER[1:0] = 00, and HSAPOL = 0. Note that the HSDC

interface sets a data bit on the HSD line at every HSCLK high to

low transition; the value of the HSIZE bit is irrelevant.

Figure 125 shows the HSDC transfer protocol for HSIZE = 0,

HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the

HSDC interface introduces a seven-cycle HSCLK gap between

every 32-bit word.

Figure 126 shows the HSDC transfer protocol for HSIZE = 1,

HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the

HSDC interface introduces a seven-cycle HSCLK gap between

every 8-bit word.

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