ADE7932 datasheet(73/120 Pages) AD

73 / 120 page

Data Sheet

ADE7978/ADE7933/ADE7932

Rev. 0 | Page 73 of 120

NO LOAD CONDITION

The no load condition is defined in metering equipment

standards as a condition where voltage is applied to the meter

but no current flows in the current circuit. To eliminate any

creep effects in the meter, the ADE7978 contains three separate

no load detection circuits: one related to the total active and

reactive powers, one related to the fundamental active and

reactive powers, and one related to the apparent power.

NO LOAD DETECTION BASED ON TOTAL ACTIVE

AND REACTIVE POWERS

The no load condition based on the total active and reactive

powers is triggered when no LSBs are accumulated in the total

active and reactive energy registers on one phase (xWATTHR and

xVARHR, x = A, B, or C) for the time specified in the APNOLOAD

and VARNOLOAD registers. In the no load condition, the total

active and reactive energies of the phase are not accumulated,

and no CFx pulses are generated based on these energies.

The equations used to compute the values of the 16-bit unsigned

registers APNOLOAD and VARNOLOAD are as follows:

PMAX

WTHR

APNOLOAD

−

(51)

PMAX

VARTHR

VARNOLOAD

−

where:

Y is the required no load current threshold computed relative

to full scale. For example, if the no load threshold current is set

10,000 times lower than the full-scale value, Y = 10,000.

WTHR and VARTHR are the values stored in the WTHR and

VARTHR registers. These values are used as the thresholds in

the first stage energy accumulators for active and reactive energy,

respectively (see the Active Energy Calculation and Reactive

Energy Calculation sections).

PMAX = 26,991,271, the instantaneous active power computed

when the ADC inputs are at full scale.

The VARNOLOAD register (Address 0xE909) usually contains

the same value as the APNOLOAD register (Address 0xE908).

When both the APNOLOAD and VARNOLOAD registers are set

to 0x0, the no load detection circuit is disabled. If the APNOLOAD

or VARNOLOAD threshold is set to 0 and the other threshold is

set to a non-zero value, the no load circuit is disabled, and the

total active and reactive powers are accumulated without any

restriction.

Bit 0 (NLOAD) in the STATUS1 register (Address 0xE503) is

set when a no load condition based on the total active or reactive

power is detected on one of the three phases. Bits[2:0]

(NLPHASE[2:0]) in the PHNOLOAD register (Address 0xE608)

indicate the state of all phases relative to a no load condition and

are set simultaneously with the NLOAD bit in the STATUS1

NLPHASE[0] indicates the state of Phase A, NLPHASE[1]

indicates the state of Phase B, and NLPHASE[2] indicates the

state of Phase C. When the NLPHASE[x] bit is cleared to 0,

Phase x is not in a no load condition. When the bit is set to 1,

Phase x is in a no load condition.

An interrupt attached to Bit 0 (NLOAD) in the STATUS1

(Address 0xE50B). When enabled, the IRQ1 pin goes low and the

status bit is set to 1 when any of the three phases enters or exits the

no load condition. To identify the phase that triggered the inter-

rupt, read the PHNOLOAD register immediately after reading

the STATUS1 register. The status bit is cleared and the IRQ1 pin

is returned high by writing a 1 to Bit 0 in the STATUS1 register.

NO LOAD DETECTION BASED ON FUNDAMENTAL

ACTIVE AND REACTIVE POWERS

The no load condition based on the fundamental active and

reactive powers is triggered when no LSBs are accumulated in

the fundamental active and reactive energy registers on one phase

(xFWATTHR and xFVARHR, x = A, B, or C) for the time specified

in the 16-bit unsigned APNOLOAD and VARNOLOAD registers.

In the no load condition, the fundamental active and reactive

energies of the phase are not accumulated, and no CFx pulses

are generated based on these energies.

APNOLOAD and VARNOLOAD are the same no load

thresholds set for the total active and reactive energies. When

both the APNOLOAD and VARNOLOAD registers are set to

0x0, the no load detection circuit is disabled. If the APNOLOAD

or VARNOLOAD threshold is set to 0 and the other threshold

is set to a non-zero value, the no load circuit is disabled, and the

fundamental active and reactive powers are accumulated without

any restriction.

Bit 1 (FNLOAD) in the STATUS1 register is set when a no load

condition based on the fundamental active or reactive power is

detected on one of the three phases. Bits[5:3] (FNLPHASE[2:0])

in the PHNOLOAD register indicate the state of all phases

relative to a no load condition and are set simultaneously with

the FNLOAD bit in the STATUS1 register.

FNLPHASE[0] indicates the state of Phase A, FNLPHASE[1]

indicates the state of Phase B, and FNLPHASE[2] indicates the

state of Phase C. When the FNLPHASE[x] bit is cleared to 0,

Phase x is not in a no load condition. When the bit is set to 1,

Phase x is in a no load condition.

An interrupt attached to Bit 1 (FNLOAD) in the STATUS1

When enabled, the IRQ1 pin goes low and the status bit is set to 1

when any of the three phases enters or exits the no load condi-

tion. To identify the phase that triggered the interrupt, read the

PHNOLOAD register immediately after reading the STATUS1

high by writing a 1 to Bit 1 in the STATUS1 register.

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