ADE7932 datasheet(63/120 Pages) AD

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Data Sheet

ADE7978/ADE7933/ADE7932

Rev. 0 | Page 63 of 120

APPARENT ENERGY CALCULATION

Apparent energy is defined as the integral of apparent power.

Apparent Energy =

∫

s(t)

(44)

The ADE7978 achieves the integration of the apparent power

signal in two stages (see Figure 81). The first stage accumulates

the instantaneous apparent power at 1.024 MHz (the DSP

computes these values at an 8 kHz rate). Each time a threshold

is reached, a pulse is generated, and the threshold is subtracted

from the internal register. The second stage consists of accumu-

lating the pulses generated at the first stage into internal 32-bit

accumulation registers. The contents of these registers are trans-

ferred to the VA-hour registers, xVAHR, when these registers

are accessed. Figure 81 illustrates this process.

The threshold is formed by concatenating the 8-bit unsigned

VATHR register (Address 0xEA04) to 27 bits equal to 0. The

VATHR register is configured by the user. Its value depends on

how much energy is assigned to one LSB of the VA-hour registers.

For example, if a derivative of the apparent energy, VAh (10n VAh,

where n is an integer) is desired as one LSB of the xVAHR

3600

PMAX

VATHR

(45)

where:

PMAX = 26,991,271 = 0x19BDAA7, the instantaneous power

computed when the ADC inputs are at full scale.

fS = 1.024 MHz, the frequency at which every instantaneous

power computed by the DSP at 8 kHz is accumulated.

VFS and IFS are the rms values of the phase voltages and currents

when the ADC inputs are at full scale.

The VATHR register is an 8-bit unsigned number, so its maxi-

mum value is 28 − 1. Its default value is 0x3. Avoid using values

lower than 3, that is, 2 or 1; never use the value 0 because the

threshold must be a non-zero value.

This discrete time accumulation or summation is equivalent

to integration in continuous time, as shown in Equation 46.

Apparent Energy =

















∑

∫

∞

→

Lim

s(nT)

s(t)dt

(46)

where:

n is the discrete time sample number.

T is the sample period.

In the ADE7978, the phase apparent powers are accumulated

in the 32-bit signed registers AVAHR, BVAHR, and CVAHR

(Address 0xE40C to Address 0xE40E). The apparent energy

and continue to increase in value when the apparent power is

positive.

The ADE7978 provides a status flag to indicate that one of the

xVAHR registers is half full. Bit 4 (VAEHF) in the STATUS0

registers changes, signifying that one of these registers is half full.

Because the apparent power is always positive and the xVAHR

registers are signed, the VA-hour registers become half full when

they increment from 0x3FFFFFFF to 0x40000000.

Setting Bit 4 (VAEHF) in the MASK0 register enables the VAEHF

interrupt. When enabled, the IRQ0 pin goes low and the status bit

is set to 1 when one of the apparent energy registers (xVAHR)

becomes half full. The status bit is cleared and the IRQ0 pin is

returned high by writing a 1 to Bit 4 (VAEHF) in the STATUS0

Setting Bit 6 (RSTREAD) in the LCYCMODE register

(Address 0xE702) enables a read with reset for all xVAHR accu-

mulation registers, that is, the registers are reset to 0 after a read

operation.

INTERNAL

ACCUMULATOR

THRESHOLD

DIGITAL SIGNAL

PROCESSOR

APGAIN

AVA

VATHR

27 26

32-BIT REGISTER

AVAHR[31:0]

AIRMS

AVRMS

Figure 81. Apparent Power Data Flow and Apparent Energy Accumulation

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