ADE7932 datasheet(74/120 Pages) AD

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ADE7978/ADE7933/ADE7932

Data Sheet

Rev. 0 | Page 74 of 120

NO LOAD DETECTION BASED ON APPARENT

POWER

The no load condition based on the apparent power is triggered

when no LSBs are accumulated in the apparent energy register

on one phase (xVAHR, x = A, B, or C) for the time specified in

the VANOLOAD register. In the no load condition, the apparent

energy of the phase is not accumulated, and no CFx pulses are

generated based on this energy.

The equation used to compute the value of the 16-bit unsigned

VANOLOAD register is as follows:

PMAX

VATHR

VANOLOAD

−

(52)

where:

Y is the required no load current threshold computed relative

to full scale. For example, if the no load threshold current is set

10,000 times lower than the full-scale value, Y = 10,000.

VATHR is the value stored in the VATHR register. This value is

used as the threshold in the first stage energy accumulator for

apparent energy (see the Apparent Energy Calculation section).

PMAX = 26,991,271, the instantaneous active power computed

when the ADC inputs are at full scale.

When the VANOLOAD register (Address 0xE90A) is set to 0x0,

the no load detection circuit is disabled.

Bit 2 (VANLOAD) in the STATUS1 register is set when a no load

condition based on apparent power is detected on one of the

three phases. Bits[8:6] (VANLPHASE[2:0]) in the PHNOLOAD

dition and are set simultaneously with the VANLOAD bit in the

STATUS1 register.

VANLPHASE[0] indicates the state of Phase A, VANLPHASE[1]

indicates the state of Phase B, and VANLPHASE[2] indicates the

state of Phase C. When the VANLPHASE[x] bit is cleared to 0,

Phase x is not in a no load condition. When the bit is set to 1,

Phase x is in a no load condition.

An interrupt attached to Bit 2 (VANLOAD) in the STATUS1

When enabled, the IRQ1 pin goes low and the status bit is set to

1 when any of the three phases enters or exits the no load condi-

tion. To identify the phase that triggered the interrupt, read the

PHNOLOAD register immediately after reading the STATUS1

high by writing a 1 to Bit 2 in the STATUS1 register.

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