ADE7932 datasheet(85/120 Pages) AD

85 / 120 page

Data Sheet

ADE7978/ADE7933/ADE7932

Rev. 0 | Page 85 of 120

If only two or three ADE7933/ADE7932 devices are used, the

DATA_B and/or DATA_N pins are connected to VDD. The

waveform samples computed by the ADE7978 that correspond

to these unconnected ADE7933/ADE7932 devices are set to full

scale. After passing through the high-pass filter, the waveform

samples are set to 0, and all quantities computed by the

ADE7978 using these samples are 0.

Bits[5:4] (CONSEL[1:0]) in the ACCMODE register (Address

0xE701) determine the way that the phase powers are computed

in the ADE7978, based on the meter configuration. For more

information, see the Energy Accumulation Modes section.

The ADE7933/ADE7932 receive a 4.096 MHz clock at the XTAL1

pin from the ADE7978 CLKOUT pin; the XTAL2 pin of the

ADE7933/ADE7932 is left open. Do not clock the ADE7933/

ADE7932 using a crystal connected between the XTAL1 and

XTAL2 pins because the ADE7933/ADE7932 devices must

function synchronously with the ADE7978; using the CLKOUT

clock of the ADE7978 ensures this synchronization.

The ADE7978 RESET_EN pin is connected to the RESET_EN

pins of all ADE7933/ADE7932 devices in the system. The

ADE7978 VT_A, VT_B, VT_C, and VT_N pins are connected

to the corresponding V2/TEMP pin of each ADE7933/ADE7932

in the system. For example, the VT_A pin of the ADE7978 is

connected to the V2/TEMP pin of the ADE7933/ADE7932 that

monitors Phase A. If the schematic does not monitor certain

phases, leave the corresponding VT_x pin of the ADE7978

unconnected. For example, the meter in the configuration

shown in Figure 105 does not monitor Phase B or the neutral

current. Therefore, the VT_B and VT_N pins are left open.

When the RESET pin of the ADE7978 is set low for at least

10 µs and then brought high again, the RESET_EN pin is set

low, and the VT_A, VT_B, VT_C, and VT_N pins toggle eight

times from high to low at a frequency of 4.096 MHz, resetting

the ADE7933/ADE7932 devices. When the RESET_EN, VT_A,

VT_B, VT_C, and VT_N pins are set high again, the reset of the

ADE7933/ADE7932 devices ends (see the Hardware Reset

section for more information).

The VT_A, VT_B, VT_C, and VT_N pins of the ADE7978 select

the signal measured by the V2 voltage ADC of the ADE7933:

either the second voltage input or the internal temperature sensor.

(The ADE7932 always measures the internal temperature sensor.)

If the VT_x signal is low, the ADC measures the input signal at

the V2P pin. If the VT_x signal is high, the ADC measures the

internal temperature sensor.

The ADE7978 reads the outputs of the ADE7933/ADE7932

using a bit stream communication composed of two signals,

SYNC and DATA. The SYNC pin of the ADE7978 is connected

to the SYNC pin of each ADE7933/ADE7932 device. The DATA

pin of each ADE7933/ADE7932 is connected to the corresponding

DATA_x pin of the ADE7978 (x = A, B, C, or N). For example,

the DATA pin of the Phase A ADE7933/ADE7932 is connected

to the DATA_A pin of the ADE7978.

If the schematic does not monitor certain phases, connect the

corresponding DATA_x pin of the ADE7978 to VDD. For

example, the meter in the configuration shown in Figure 105

does not monitor Phase B or the neutral current. Therefore, the

DATA_B and DATA_N pins of the ADE7978 are tied to VDD.

The SYNC pin of the ADE7978 generates a 1.024 MHz serial clock

to the ADE7933/ADE7932 slaves. Each ADE7933/ADE7932

responds with a bit stream generated by the first stage of the

ADE7933/ADE7932 ADCs (see the Bit Stream Communication

Between the ADE7978 and the ADE7933/ADE7932 section).

ADE7978 QUICK SETUP AS AN ENERGY METER

An energy meter is usually characterized by the nominal current

(In), nominal voltage (Vn), nominal frequency (fn), and the meter

constant (MC). To quickly set up the ADE7978, follow these steps:

1. If fn = 60 Hz, set Bit 14 (SELFREQ) to 1 in the COMPMODE

bit at 0, the default value.

2. Initialize the CF1DEN, CF2DEN, and CF3DEN registers

(Address 0xE611 to Address 0xE613) based on the following

equation:

CFxDEN

]

imp/kwh

[

103

For more information, see the Energy-to-Frequency

Conversion section.

3. Initialize the WTHR, VARTHR, and VATHR registers

(Address 0xEA02 to Address 0xEA04) based on the

following equation:

WTHR, VARTHR, and VATHR =

3600

PMAX

For more information, see the Active Energy Calculation

section, the Reactive Energy Calculation, and the Apparent

Energy Calculation section.

4. Initialize the VLEVEL register (Address 0x43A2) based on

the following equation:

VLEVEL = VFS/Vn × 4 × 106

For more information, see the Fundamental Active Power

Calculation section.

5. Initialize the VNOM register based on the following equation:

VNOM = V/VFS × 3,761,808

For more information, see the Apparent Power Calculation

Using VNOM section.

6. Enable the data memory RAM protection by writing 0xAD

to the internal 8-bit register located at Address 0xE7FE, fol-

lowed by a write of 0x80 to the internal 8-bit register located

at Address 0xE7E3.

7. Start the DSP by writing 0x0001 to the run register

(Address 0xE228).

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