ADE7932 datasheet(53/120 Pages) AD

53 / 120 page

Data Sheet

ADE7978/ADE7933/ADE7932

Rev. 0 | Page 53 of 120

–10

–20

–30

–40

0.1

FREQUENCY (Hz)

Figure 74. Frequency Response of the LPF Used to Filter Instantaneous Power

in Each Phase: LPFSEL Bit of CONFIG Register Set to 1

The ADE7978 stores the instantaneous total phase active

powers in the 24-bit AWATT, BWATT, and CWATT registers

(Address 0xE518 to Address 0xE51A). To calculate the value

of these registers, use the following equation:

∑

∞

xWATT

cos(φk − γk) × PMAX × 4

(27)

where:

VFS and IFS are the rms values of the phase voltage and current

when the ADC inputs are at full scale.

PMAX = 26,991,271, the instantaneous power computed when

the ADC inputs are at full scale and in phase.

The xWATT[23:0] waveform registers can be accessed using

any of the serial port interfaces. For more information, see the

Waveform Sampling Mode section.

FUNDAMENTAL ACTIVE POWER CALCULATION

The ADE7978 computes the fundamental active power using a

proprietary algorithm that requires initialization of the network

frequency and of the nominal voltage measured in the voltage

channel. Bit 14 (SELFREQ) in the COMPMODE register

(Address 0xE60E) must be set according to the frequency of the

network in which the ADE7978 is connected. If the network

frequency is 50 Hz, clear this bit to 0 (the default value). If the

network frequency is 60 Hz, set this bit to 1.

To initialize the nominal voltage measured in the voltage channel,

configure the 28-bit signed VLEVEL register (Address 0x43A2)

with a positive value based on the following equation:

4 ×

VLEVEL

(28)

where:

VFS is the rms value of the phase voltages when the ADC inputs

are at full scale.

Vn is the rms nominal value of the phase voltage.

Table 20 provides the settling time for the fundamental active

power measurement. The settling time is the time required for

the power to reflect the value at the input of the ADE7978.

Table 20. Settling Time for Fundamental Active Power

Input Signal

Settling Time (ms)

63% PMAX

375

100% PMAX

875

The serial ports of the ADE7978 work with 32-, 16-, or 8-bit

words, whereas the DSP works with 28-bit words. The 28-bit

signed VLEVEL register is transmitted as a 32-bit register with

the four most significant bits padded with 0s (see Figure 75).

28 27

28-BIT NUMBER

0000

Figure 75. 28-Bit VLEVEL Register Transmitted as a 32-Bit Word

ACTIVE POWER GAIN CALIBRATION

The average active power result from the LPF2 output in each

phase can be scaled by ±100% by writing to the 24-bit watt

gain register for each phase: APGAIN, BPGAIN, or CPGAIN

(Address 0x4399 to Address 0x439B). Because all power datapaths

have identical overall gains, the xPGAIN registers are used with

the datapaths of all powers computed by the ADE7978: total

active and reactive powers, fundamental active and reactive

powers, and apparent powers. Therefore, to compensate the

gain errors in the datapaths of various powers, it is sufficient to

analyze only one power datapath (for example, the total active

power) and calculate the corresponding APGAIN, BPGAIN,

and CPGAIN register values.

The power gain registers are twos complement signed registers

with a resolution of 2−23/LSB. Equation 29 describes mathemat-

ically the function of the power gain registers.

Average Power Data =

(29)













Gain

Power

Output

LPF2

The output is decreased by 50% by writing 0xC00000 to the

watt gain registers; the output is increased by 50% by writing

0x400000 to the watt gain registers. These registers are used to

calibrate the active, reactive, and apparent power (or energy)

calculation for each phase.

The serial ports of the ADE7978 work with 32-, 16-, or 8-bit

words, whereas the DSP works with 28-bit words. Like the

xIGAIN registers shown in Figure 44, the 24-bit APGAIN,

BPGAIN, and CPGAIN registers are sign extended to 28 bits

and padded with four 0s for transmission as 32-bit registers.

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